Datasheet

MAX536/MAX537
SS is an input intended for use in a multimaster environ-
ment. However, SS or unused PORT D bit RXD, TXD, or
possibly MISO (if DAC readback is not used) should be
configured as a general-purpose output and used as CS by
setting the appropriate Data Direction Register bit.
The SPCR configuration (memory location $1028) is shown
below:
When MSTR = 1 in the SPCR, a write to the Serial
Peripheral Data I/O Register (SPDR), located at memory
location $102A, initiates the transmission/reception of
data. The data transfer is monitored and the appropri-
ate flags are set in the Serial Peripheral Status
Register (SPSR).
The SPSR configuration is shown below:
An example of 68HC11 programming code for a
two-byte SPI transfer to the MAX536/MAX537 is given in
Table 4. SS is used for CS, the high byte of MAX536/
MAX537 digital data is stored in memory location $0100,
and the low byte is stored in memory location $0101.
Interfacing to Other Controllers
When using MICROWIRE, refer to the section on Inter-
facing to the M68HC11 for guidance, since MICROWIRE
can be considered similar to SPI when CPOL = 0 and
CPHA = 0. When interfacing to Intel’s 80C51/80C31
microcontroller family, use bit-pushing to configure a
desired port as the MAX536/MAX537 interface port. Bit-
pushing involves arbitrarily assigning I/O port bits as
interface control lines, and then writing to the port each
time a signal transition is required.
Unipolar Output
For a unipolar output, the output voltages and the reference
inputs are the same polarity. Figure 10 shows the
MAX536/MAX537 unipolar output circuit, which is also the typ-
ical operating circuit. Table 5 lists the unipolar output codes.
Bipolar Output
The MAX536/MAX537 outputs can be configured for
bipolar operation using Figure 11’s circuit. One op amp
and two resistors are required per DAC. With R1 = R2:
V
OUT
= V
REF
[(2N
B
/4096) - 1]
where N
B
is the numeric value of the DAC’s binary input
code. Table 6 shows digital codes and corresponding
output voltages for Figure 11’s circuit.
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
20 ______________________________________________________________________________________
DAC CONTENTS
ANALOG OUTPUT
MSB LSB
4095
1111 1111 1111 +V
REF
( ——— )
4096
2049
1000 0000 0001 +V
REF
( ——— )
4096
2048 +V
REF
1000 0000 0000 +V
REF
( ——— ) = ————
4096 2
2047
0111 1111 1111 +V
REF
( ——— )
4096
1
0000 0000 0001 +V
REF
( ——— )
4096
0000 0000 0000 0V
DAC CONTENTS
ANALOG OUTPUT
MSB LSB
2047
1111 1111 1111 +V
REF
( ——— )
2048
1
1000 0000 0001 +V
REF
( ——— )
2048
1000 0000 0000 0V
1
0111 1111 1111 -V
REF
( ——— )
2048
2047
0000 0000 0001 -V
REF
( ——— )
2048
2048
0000 0000 0000 -V
REF
( ——— ) = -V
REF
2048
Table 5. Unipolar Code Table
Table 6. Bipolar Code Table
NOTE: 1 LSB = (V
REF
) (
4096
)
1
BIT
76543210
NAME
SPIE SPE DWOM MSTR CPOL CPHA SPR1 SPR0
SETTING AFTER RESET
00 0 0 0 1 U
*
U
*
SETTING FOR TYPICAL SPI COMMUNICATION
0101000
**
1
**
*U = Unknown
**Depends on µP clock frequency.
Always configure the 68HC11 as the “master” controller
and the MAX536/MAX537 as the “slave” device.
BIT
7654 321 0
NAME
SPIF WCOL – MODF – – – –
RESET CONDITIONS
0000 000 0