Datasheet

9Maxim Integrated
MAX5318
18-Bit, High-Accuracy Voltage Output DAC with
Digital Gain, Offset Control, and SPI Interface
DIGITAL INTERFACE ELECTRICAL CHARACTERISTICS
(V
AVDD
= 5V, V
DDIO
= 1.8V to 2.7V, V
AVSS
= -1.25V, V
REF
= 4.096V, R
L
= 10kω, TC/SB = M/Z = DGND, C
REFO
= 100pF, C
BYPASS
= 1µF, T
A
= -40°C to +105°C, unless otherwise noted. Typical values are at T
A
= +25°C.)(GAIN = 0x3FFFF and OFFSET = 0x00000.)
(Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DIGITAL INPUTS (SCLK, DIN, CS, LDAC, M/Z, RST)
Input High Voltage V
IH
0.8 x
V
DDIO
V
Input Low Voltage V
IL
0.2 x
V
DDIO
V
Input Hysteresis (Note 4) V
IHYST
200 300 mV
Input Leakage Current I
IN
Input = 0V at V
DDIO
Q0.1 Q1 FA
Input Capacitance C
IN
10 pF
DIGITAL OUTPUTS CHARACTERISTICS (DOUT, READY, BUSY)
Output Low Voltage V
OL
I
SOURCE
= 1.0mA 0.2 V
Output High Voltage V
OH
I
SINK
= 1.0mA, except for BUSY
V
DDIO
- 0.2
V
Output Three-State Leakage I
OZ
DOUT only
Q0.1 Q1 FA
Output Three-State Capacitance C
OZ
DOUT only 15 pF
Output Short-Circuit Current I
OSS
V
DDIO
= 2.7V
Q150
mA
TIMING CHARACTERISTICS
Serial Clock Frequency f
SCLK
Stand-alone write mode 50
MHz
Stand-alone read mode and daisy-
chained read and write modes (Note 6)
8
SCLK Period t
CP
Stand-alone write mode 20
ns
Stand-alone read mode and daisy-
chained read and write modes
125
SCLK Pulse-Width High t
CH
40% duty cycle 9 ns
SCLK Pulse-Width Low t
CL
40% duty cycle 9 ns
CS
Fall to SCLK Fall Setup Time
t
CSSO
First SCLK
falling edge
Stand-alone write mode 12
ns
Stand-alone read mode
and daisy-chained read
and write modes
72
CS Fall to SCLK Fall Hold Time
t
CSH0
Inactive falling edge preceding first
falling edge
0 ns
SCLK Fall to CS Rise Hold Time
t
CSH1
24th falling edge 4 ns
DIN to SCLK Fall Setup Time t
DS
8 ns
DIN to SCLK Fall Hold Time t
DH
8 ns
SCLK Rise to DOUT Settle Time t
DOT
C
L
= 20pF (Note 7) 40 ns
SCLK Rise to DOUT Hold Time t
DOH
C
L
= 0pF (Note 7) 2 ns