Datasheet

8Maxim Integrated
MAX5318
18-Bit, High-Accuracy Voltage Output DAC with
Digital Gain, Offset Control, and SPI Interface
DIGITAL INTERFACE ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= 5V, V
DDIO
= 2.7V to 5.5V, V
AVSS
= -1.25V, V
REF
= 4.096V, R
L
= 10kω, TC/SB = M/Z = DGND, C
REFO
= 100pF, C
BYPASS
= 1µF, T
A
= -40°C to +105°C, unless otherwise noted. Typical values are at T
A
= +25°C.)(GAIN = 0x3FFFF and OFFSET = 0x00000.)
(Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TIMING CHARACTERISTICS
Serial Clock Frequency f
SCLK
Stand-alone, write mode 50
MHz
Stand-alone, read mode and daisy-
chained read and write modes (Note 5)
12.5
SCLK Period t
CP
Stand-alone, write mode 20
ns
Stand-alone, read mode and daisy-
chained read and write modes
80
SCLK Pulse Width High t
CH
40% duty cycle 8 ns
SCLK Pulse Width Low t
CL
40% duty cycle 8 ns
CS Fall to SCLK Fall Setup Time
t
CSSO
First SCLK
falling edge
Stand-alone, write mode 8
ns
Stand-alone, read mode
and daisy-chained read
and write modes
38
CS Fall to SCLK Fall Hold Time
t
CSH0
Inactive falling edge preceding first falling
edge
0 ns
SCLK Fall to CS Rise Hold Time
t
CSH1
24th falling edge 2 ns
DIN to SCLK Fall Setup Time t
DS
5 ns
DIN to SCLK Fall Hold Time t
DH
4.5 ns
SCLK Rise to DOUT Settle Time t
DOT
C
L
= 20pF (Note 6) 32 ns
SCLK Rise to DOUT Hold Time t
DOH
C
L
= 0pF (Note 6) 2 ns
SCLK Fall to DOUT Disable Time t
DOZ
24th active edge deassertion 2 30 ns
CS Fall to DOUT Enable
t
DOE
Asynchronous assertion 2 30 ns
CS Rise to DOUT Disable
t
CSDOZ
Stand-alone, aborted sequence 35
ns
Daisy-chained, aborted sequence 70
SCLK Fall to READY Fall
t
CRF
24th falling-edge assertion, C
L
= 20pF 30 ns
SCLK Fall to READY Hold
t
CRH
24th falling-edge assertion, C
L
= 0pF 2 ns
SCLK Fall to BUSY Fall
t
CBF
BUSY assertion
5 ns
CS Rise to READY Rise
t
CSR
C
L
= 20pF 35 ns
CS Rise to SCLK Fall
t
CSA
24th falling edge, aborted sequence 20 ns
CS Pulse Width High
t
CSPW
Stand alone 20 ns
SCLK Fall to CS Fall
t
CSF
24th falling edge 100 ns
LDAC Pulse Width
t
LDPW
20 ns
LDAC Fall to SCLK Fall Hold
t
LDH
Last active falling edge 20 ns
RST Pulse Width
t
RSTPW
20 ns