Datasheet
6Maxim Integrated
MAX5318
18-Bit, High-Accuracy Voltage Output DAC with
Digital Gain, Offset Control, and SPI Interface
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
DDIO
= 2.7V to 3.3V, V
AVSS
= -1.25V, V
AGND
= V
DGND
= V
AGND_F
= V
AGND_S
= 0V, V
REF
= 2.5V, TC/SB = PD = LDAC =
M/Z = DGND, RST = V
DDIO
, C
REFO
= 100pF, C
L
= 100pF, R
L
= 10kω, C
BYPASS
= 1µF, GAIN = 0x3FFFF, OFFSET = 0x00000,
T
A
= -40°C to +105°C, unless otherwise noted. Typical values are at T
A
= +25°C.) (GAIN = 0x3FFFF and OFFSET = 0x00000.)(Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DC Power-Supply Rejection DCPSRR
V
OUT
at full scale, V
AVDD
= 2.7V to 3.3V -2.5 Q0.4 +2.5
LSB/V
V
AVSS
= -1.5V to -0.5V -2.5 Q0.04 +2.5
STATIC PERFORMANCE—VOLTAGE REFERENCE INPUT SECTION
Reference High Input Range V
REF
2.4
V
AVDD
-
0.1
V
Reference Input Capacitance C
REF
10 pF
Reference Input Resistance R
REF
10 MI
Reference Input Current IB Q0.15 FA
STATIC PERFORMANCE—VOLTAGE REFERENCE OUTPUT SECTION
Reference High Output Range 2.4
V
AVDD
-
0.1
V
Reference High Output Load
Regulation
500 ppm/mA
Reference Output Capacitor R
ESR
< 5I 0.1 nF
STATIC PERFORMANCE—V
BYPASS
OUT SECTION
Output Voltage V
BYPASS
2.3 2.4 2.5 V
Load Capacitance to GND C
L
Required for stability, R
ESR
= 0.1I (typ) 1 8 FF
POWER-SUPPLY REQUIREMENTS
Positive Analog Power-Supply
Range
V
AVDD
2.7 3.3 V
Interface Power-Supply Range V
DDIO
1.8 5.5 V
Negative Analog Power-Supply
Range
V
AVSS
-1.5 -1.25 0 V
Positive Analog Power-Supply
Current
I
AVDD
No load, external reference, output at zero
scale
5.0 6.5 mA
Negative Analog Power-Supply
Current
I
AVSS
No load, external reference, output at zero
scale
-1.5 -0.8 mA
Interface Power-Supply Current I
VDDIO
Digital inputs at V
DDIO
or DGND 0.2 5.0 FA
Positive Analog Power-Supply
Power-Down Current
PD = V
DDIO
, power-down mode 20 50 FA
Negative Analog Power-Supply
Power-Down Current
PD = V
DDIO
, power-down mode -5 -2 FA
DYNAMIC PERFORMANCE
Voltage Output Slew Rate SR
From 10% to 90% full scale, positive and
negative transitions
4.9 V/Fs
Voltage Output Settling Time t
S
From falling edge of LDAC to within
0.003% FS, R
L
= 10kI, DIN = 04000h
(6.25% FS) to 3C000h (93.75% FS)
3 Fs