Datasheet

38Maxim Integrated
MAX5318
18-Bit, High-Accuracy Voltage Output DAC with
Digital Gain, Offset Control, and SPI Interface
Voltage Reference Selection and Layout
The voltage reference should be placed close to the DAC.
The same power-supply decoupling and grounding rules
as the DAC should be implemented. Many voltage refer-
ences require an output capacitor for stability or noise
reduction. Provided the trace between the reference
device and the DAC is kept short and well shielded, a sin-
gle capacitor may be used and placed close to the DAC.
However, for improved noise immunity, additional capaci-
tors may be used but be careful not to exceed the recom-
mended capacitance range for the voltage reference.
Refer to Maxim Applications Note AN4300: Calculating
the Error Budget in Precision Digital-to-Analog Converter
(DAC) Applications for detailed description of voltage
reference parameters and trading off the error budget.
The MAX6126 is recommended for use with this device.
Optimizing Data Throughput Rate
The LDAC and BUSY Interaction section details the tim-
ing of data written to the device and how the DAC is
updated. Data throughput speed can be increased by
overlapping the data load time with the calibration and
settling time as shown below in Figure 12. Following the
24th SCLK falling edge, the device starts its calibration
period. Providing that the LDAC falling edge arrives
before the 24th SCLK falling edge, and assuming the SPI
clock frequency is high enough, the throughput period is
therefore limited by the internal calculation and settling
times only. A slight further increase in throughput time
can be gained by either toggling LDAC during the cal-
culation time or by pulling it low permanently. However,
the exact point at which the DAC update occurs is then
determined internally as indicated by the BUSY line rising
edge. This is not an exact time.
BUSY Line Pullup Resistor Selection
The BUSY pin is an open-drain output. It therefore
requires a pullup resistor. 2kI value is recommended as
a compromise between power and speed. Stray capaci-
tance on this line can easily slow the rise time to an
unacceptable level. The BUSY pin can sink up to 5mA.
Therefore a resistor as low as V
DDIO
/0.005 may be used
if faster rise times are required.
Producing Unipolar High-Voltage
and Bipolar Outputs
Figure 11 and Figure 12 show how external op amps can
be used to produce a unipolar high-voltage output and
a bipolar output
Definitions
Integral Nonlinearity (INL)
INL is the deviation of the measured transfer function from
a straight line drawn between two codes. This line is drawn
between the zero and full-scale codes of the transfer func-
tion, once offset and gain errors have been nullified.
Differential Nonlinearity (DNL)
DNL is the difference between an actual step height and
the ideal value of 1 LSB. If the magnitude of the DNL is
less than or equal to 1 LSB, the DAC guarantees no miss-
ing codes and is monotonic.
Figure 12. Optimum Throughput with Stable Update Period
24TH SCLK
DIN
OUT
BUSY
t
BUSY
LDAC
24TH SCLK
LDAC FALLING EDGE BEFORE 24TH SCLK FALLING EDGE