Datasheet

10Maxim Integrated
MAX5318
18-Bit, High-Accuracy Voltage Output DAC with
Digital Gain, Offset Control, and SPI Interface
DIGITAL INTERFACE ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= 5V, V
DDIO
= 1.8V to 2.7V, V
AVSS
= -1.25V, V
REF
= 4.096V, R
L
= 10kω, TC/SB = M/Z = DGND, C
REFO
= 100pF, C
BYPASS
= 1µF, T
A
= -40°C to +105°C, unless otherwise noted. Typical values are at T
A
= +25°C.)(GAIN = 0x3FFFF and OFFSET = 0x00000.)
(Note 2)
Figure 1. Serial Interface Timing Diagram, Stand-Alone Operation
Note 2:
All devices are 100% tested at T
A
= +25°C and T
A
= +105°C. Limits at T
A
= -40°C are guaranteed by design.
Note 3:
Linearity is tested from V
REF
to AGND.
Note 4: Guaranteed by design.
Note 5: The total analog throughput time from DIN to V
OUT
is the sum of t
S
and t
BUSY
(4.9µs, typ).
Note 6:
Daisy-chain speed is relaxed to accommodate (t
CRF
+ t
CSS0
).
Note 7: DOUT speed limits overall SPI speed..
R3
12
t
CSSO
345678 21 22 23 24 25
DIN
SCLK
t
CSH0
R2 R1 R0 D17 D16 D15 D14 D1 D0 X––
0R3 R2 R1 R0 D17 D16 D15 D2 D1 D0 0 ZDOUT
CS
Z
t
CSH1
t
CSA
t
DS
t
DH
t
CP
t
CL
t
CH
t
DOH
t
DOT
t
DOE
t
CSPW
t
DOZ
t
CRH
t
CSF
t
CRF
t
CSR
READY
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCLK Fall to DOUT Disable Time t
DOZ
24th active edge deassertion 2 40 ns
CS Fall to DOUT Enable
t
DOE
Asynchronous assertion 2 50 ns
CS Rise to DOUT Disable
t
CSDOZ
Stand-alone, aborted sequence 70
ns
Daisy-chained, aborted sequence 130
SCLK Fall to READY Fall
t
CRF
24th falling edge assertion, C
L
= 20pF 60 ns
SCLK Fall to READY Hold
t
CRH
24th falling edge assertion, C
L
= 0pF 2 ns
SCLK Fall to BUSY Fall
t
CBF
BUSY assertion
5 ns
CS Rise to READY Rise
t
CSR
C
L
= 20pF 60 ns
CS Rise to SCLK Fall
t
CSA
24th falling edge, aborted sequence 20 ns
CS Pulse Width High
t
CSPW
Stand alone 20 ns
SCLK Fall to CS Fall
t
CSF
24th falling edge 100 ns
LDAC Pulse Width
t
LDPW
20 ns
LDAC Fall to SCLK Fall Hold
t
LDH
Last active falling edge 20 ns
RST Pulse Width
t
RSTPW
20 ns