Datasheet

MAX5312
±10V, 12-Bit, Serial, Voltage-Output DAC
6 _______________________________________________________________________________________
TIMING CHARACTERISTICS
(V
DD
= +15V, V
SS
= -15V or 0V, V
CC
= +2.7V to +5.5V, AGND = DGND = SGND = 0, V
REF
= 5V, R
LOAD
= 2kΩ, C
LOAD
= 250pF, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCLK Frequency 10 MHz
SCLK Clock Period t
CP
100 ns
SCLK Pulse-Width High t
CH
For nondaisy-chain use 45 ns
SCLK Pulse-Width Low t
CL
For nondaisy-chain use 45 ns
CS Fall to SCLK Rise Setup Time t
CSS
40 ns
+2.7V ≤ V
CC
≤ +3.6V 15
SCLK Rise to CS Rise Hold Time t
CSH
+4.5V ≤ V
CC
≤ +5.5V 10
ns
DIN Setup Time t
DS
20 ns
DIN Hold Time t
DH
10 ns
LDAC Pulse Width t
LD
50 ns
+2.7V ≤ V
CC
≤ +3.6V 100
CS Rise to LDAC Low Setup Time t
LDS
+4.5V ≤ V
CC
≤ +5.5V 50
ns
C
LOAD
= 20pF, +2.7V ≤ V
CC
≤ +3.6V 100
SCLK Fall to DOUT Valid
Propagation Delay
t
DO1
C
LOAD
= 20pF, +4.5V ≤ V
CC
≤ +5.5V 80
ns
SCLK Rise to CS Fall Delay t
CS0
10 ns
CS Low to DOUT Valid Time t
CSE
C
LOAD
= 20pF 120 ns
CS High to DOUT Disabled Time t
CSD
120 ns
CS Rise to SCLK Rise Hold Time t
CS1
50 ns
+2.7V ≤ V
CC
≤ +3.6V 200
CS Pulse-Width High t
CSW
+4.5V ≤ V
CC
≤ +5.5V 100
ns
CLR Pulse-Width Low t
CLR
50 ns
Note 1: Output unloaded, digital inputs = V
CC
or DGND.
Note 2: ΔV
DD
= +14.5V to +15.5V, ΔV
SS
= -15.5V to -14.5V, code = FFF.
Note 3: Measured from code 14hex to FFFhex.