Datasheet

20ns before the next write sequence since a write

sequence is initiated on a falling edge of CS. If CS

goes high prior to completing 16 cycles of SCLK, the

input data is discarded. To initiate a new data transfer,

drive CS low again. The serial clock (SCLK) can be

either high or low between CS write pulses. Figure 4

shows the timing diagram for the complete 3-wire serial

interface transmission.

The MAX5308/MAX5309 digital inputs are double-

buffered. Depending on the command issued through

the serial interface, the input register(s) can be loaded

without affecting the DAC register(s), the DAC regis-

ter(s) can be loaded directly, or all eight registers can

be updated simultaneously from the input registers.

MAX5308/MAX5309

Low-Power, Low-Glitch, Octal 10-Bit Voltage-

Output DACs with Serial Interface

_______________________________________________________________________________________ 9

INPUT

DAC

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

OUT8

SCLK

DIN

(MAX5309) CLR

REF

LDAC

(MAX5308) DOUT

INPUT

DAC

SERIAL

TO PARALLEL

SHIFT REGISTER

MAX5308

MAX5309

GND

Figure 1. Functional Diagram