Datasheet

Detailed Description
The MAX5308/MAX5309 are 10-bit, eight-channel, low-
power, voltage-output digital-to-analog converters
(DACs) that are easily addressed using a simple 3-wire
serial interface. These devices feature eight double-
buffered DACs using a common 16-bit serial to parallel
shift register, a power-on reset (POR) circuit and eight
output buffer amplifiers.
Figure 1 shows the block diagram of MAX5308/
MAX5309 . The shift register converts a serial 16-bit
word to parallel data for each input register operating
with a clock rate of up to 15MHz. The 3-wire digital
interface to the shift register consists of chip-select
(CS), serial clock (SCLK), and data input (DIN). Serial
data at DIN is loaded on the falling edge of SCLK.
The eight double-buffered DACs consist of input and
DAC registers. The input registers are directly connect-
ed to the shift register and hold the result of the most
recent write operation. The eight 10-bit DAC registers
hold the current output code for the respective DAC.
Data can be transferred from the input registers to the
DAC registers by either the hardware interface (LDAC)
or by software command. The output of DACs are
buffered through eight Rail-to-Rail
®
op amps.
The MAX5308 has a digital output (DOUT) which can
be used to daisy chain multiple devices on a single ser-
ial bus. The MAX5309 contains a hardware shutdown
(CLR) to clear all internal registers and power-down all
DACs.
The MAX5308/MAX5309 require an external reference
such as the MAX6161 family. The reference voltage
range is from 0.8V to V
DD
.
POR circuitry gives the DACs a defined state during
start-up. At power-on, the DAC outputs reset to zero
through a 100kΩ resistor, providing additional safety for
applications that drive valves or other transducers that
need to be off at power-up.
The MAX5308/MAX5309 feature low digital feedthrough
and minimize glitch energy on MSB transitions. The 3-
wire SPI, QSPI, MICROWIRE and DSP-compatible seri-
al interface saves additional circuit board space
Serial Interface
Configuration
The MAX5308/MAX5309 3-wire serial interface are
compatible with MICROWIRE, SPI, QSPI, and DSPs
(Figure 2 and Figure 3). The chip-select input (CS)
frames the serial data loading at DIN. Following CS’s
high-to-low transition, the data is shifted synchronously
and latched into the input register on each falling edge
of the serial clock input (SCLK). Each serial word is 16
bits, the first four bits are the control word followed by
10 data bits (MSB first) as shown in Table 1. The last
two data bits must be zeros. The 10-bit DAC code is
unipolar binary with 1LSB = V
REF
/1024.
The serial input register transfers its contents to the
input registers after loading 16 bits of data and driving
CS high. CS must be brought high for a minimum of
MAX5308/MAX5309
Low-Power, Low-Glitch, Octal 10-Bit Voltage-
Output DACs with Serial Interface
_______________________________________________________________________________________ 7
Pin Description
PIN NAME FUNCTION
1 SCLK Serial Clock Input. Serial data is loaded on the falling edge of SCLK.
2 DIN Serial Data Input
3 LDAC
Load DAC. LDAC is an asynchronous active-low input that updates the DAC outputs
simultaneously. If LDAC is driven low, the DAC registers are transparent.
4 REF Reference Voltage Input
5–12 OUT_ Analog Output Signal
13 GND Ground
14 V
DD
Power Supply. Bypass V
DD
to GND with a 0.1µF capacitor.
DOUT Data Output (MAX5308). DOUT is updated on the falling edge of SCLK.
15
CLR
Asynchronous Clear DAC (MAX5309). Active-low input to clear all DACs and registers. Resets all
outputs to zero.
16 CS Chip-Select Input (active-low)
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.