Datasheet

MAX5308/MAX5309
Low-Power, Low-Glitch, Octal 10-Bit Voltage-
Output DACs with Serial Interface
12 ______________________________________________________________________________________
where D is the decimal value of the DACs’ binary input
code. Table 4 shows digital codes (offset binary) and
corresponding output voltages for the Figure 7 circuit.
Power-Supply Considerations
On power-up, all input and DAC registers are cleared
and DOUT is low.
Bypass V
DD
to GND with a 4.7µF capacitor in parallel
with a 0.1µF capacitor. Use short lead lengths and
place the bypass capacitors as close to the supply
pins as possible.
SCLK X 1 2 3 4 16
D1D12D14X X
X
DIN
X X
DOUT
D14* D13* D12* D1*
CS
t
CSH
t
CL
t
DH
t
DS
t
CSS
t
CH
t
SDL
t
SDH
t
CSPWH
D0
D0*
D15*
D15 D13
*PREVIOUS INPUT DATA
±0.5LSB
V
OUT
_
t
CLRPWL
t
LDACPWL
t
S
CLR
LDAC
Figure 4. Timing Diagram