Datasheet

MAX5306/MAX5307
Power-Supply Considerations
On power-up, all input and DAC registers are cleared
and DOUT is in low.
Bypass V
DD
to GND with a 4.7µF capacitor in parallel
with a 0.1µF capacitor. Use short lead lengths and
place the bypass capacitors as close to the supply
pins as possible.
Low-Power, Low-Glitch, Octal 12-Bit Voltage-
Output DACs with Serial Interface
12 ______________________________________________________________________________________
SCLK X 1 2 3 4 16
D1D12D14X X
X
DIN
X X
DOUT
D14* D13* D12* D1*
CS
t
CSH
t
CL
t
DH
t
DS
t
CSS
t
CH
t
SDL
t
SDH
t
CSPWH
D0
D0*
D15*
D15 D13
*PREVIOUS INPUT DATA
±0.5LSB
V
OUT
_
t
CLRPWL
t
LDACPWL
t
S
CLR
LDAC
Figure 4. Timing Diagram
DAC CONTENTS
ANALOG OUTPUT
MSB LSB
2047
1111 1111 1111 +V
REF
( ——— )
2048
1
1000 0000 0001 +V
REF
( ——— )
2048
1000 0000 0000 0V
1
0111 1111 1111 -V
REF
( ——— )
2048
2047
0000 0000 0001 -V
REF
( ——— )
2048
2048
0000 0000 0000 -V
REF
( ——— )= -V
REF
2048
DAC CONTENTS
ANALOG OUTPUT
MSB LSB
4095
1111 1111 1111 +V
REF
( ——— )
4096
2049
1000 0000 0001 +V
REF
( ——— )
4096
2048 +V
REF
1000 0000 0000 +V
REF
( ——— )= ————
4096 2
2047
0111 1111 1111 +V
REF
( ——— )
4096
1
0000 0000 0001 +V
REF
( ——— )
4096
0000 0000 0000 0V
Table 3. Unipolar Code Table Table 4. Bipolar Code Table