Datasheet

MAX5290–MAX5295

Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,

Voltage-Output DACs

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Pin Description

MAX5290

MAX5292

MAX5294

MAX5291

MAX5293

MAX5295

THIN QFN

TSSOP

THIN QFN

TSSOP

NAME FUNCTION

1213DSP

Clock Enable. Connect DSP to DV

at power-up to transfer

data on the rising edge of SCLK. Connect DSP to DGND at

power-up to transfer data on the falling edge of SCLK.

2 3 2 4 DIN Serial Data Input

3435CS Active-Low Chip-Select Input

4 5 4 6 SCLK Serial Clock Input

5657DV

Digital Supply

6 7 6 8 DGND Digital Ground

7 8 7 9 AGND Analog Ground

89810AV

Analog Supply

9 10 9 11 OUTB DACB Output

— — 10 12 FBB Feedback for DACB Output Buffer

10 11 11 13 REF Reference Input

— — 12 14 FBA Feedback for DACA Output Buffer

11, 13 — — — N.C. No Connection. Not internally connected.

12 12 13 15 OUTA DACA Output

14 13 14 16 PU

Power-Up State Select Input. Connect PU to DV

to set OUTA

and OUTB to full scale upon power-up. Connect PU to DGND to

set OUTA and OUTB to zero upon power-up. Leave PU floating

to set OUTA and OUTB to midscale upon power-up.

15 14 15 1 UPIO2 User-Programmable Input/Output 2

16 1 16 2 UPIO1 User-Programmable Input/Output 1

————EP

Exposed Paddle (QFN Only). Not internally connected. Do not

connect to circuitry.