Datasheet

Serial Interface
The 3-wire serial interface (SPI, QSPI, and MICROWIRE
compatible) used in the MAX5234/MAX5235 allows for
complete control of DAC operations (Figures 4 and 5).
Figures 1 and 2 show the timing for the serial interface.
The serial word consists of 3 control bits followed by 12
data bits (MSB first) and 1 sub-bit as described in
Tables 1, 2, and 3. When the 3 control bits are all zero
or all 1, D11–D8 are used as additional control bits,
allowing for greater DAC functionality.
The digital inputs allow any of the following: loading the
input register(s) without updating the DAC register(s),
updating the DAC register(s) from the input register(s),
or updating the input and DAC register(s) simultane-
ously. The control bits and D11–D8 allow the DACs to
operate independently.
Send the 16-bit data as one 16-bit word (QSPI) or two
8-bit packets (SPI and MICROWIRE), with CS low dur-
ing this period. The control bits and D11–D8 determine
which registers update and the state of the registers
when exiting shutdown. The 3-bit control and D11–D8
determine the following:
• Registers to be updated
• Selection of the power-down modes
The general timing diagram of Figure 1 illustrates data
acquisition. Driving CS low enables the device to
receive data. Otherwise, the interface control circuitry is
disabled. With CS low, data at DIN is clocked into the
MAX5234/MAX5235
Single-Supply 3V/5V, Voltage-Output, Dual,
Precision 12-Bit DACs
______________________________________________________________________________________ 11
CS
SCLK
DIN
COMMAND EXECUTED
9
8
16 (1)
1
C1
C2 S0
C0
D11
D10
D9
D8 D5 D4 D3 D2 D1 D0D7 D6
Figure 1. Serial Interface Timing
CS
SCLK
DIN
t
CSW
t
CS1
t
CSH
t
CSS
t
CSO
t
CH
t
CL
t
CP
t
DS
t
DH
t
LDL
LDAC
t
CSLD
Figure 2. Detailed Serial Interface Timing