Datasheet

3Maxim Integrated
14-/16-Bit, Low-Power, Buffered Output,
Rail-to-Rail DACs with SPI Interface
MAX5214/MAX5216
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 2.7V to 5.5V, V
REF
= 2.5V to V
DD
, C
L
= 60pF, R
L
= 10kI, T
A
= -40NC to +105NC, unless otherwise noted. Typical values are
at T
A
= +25NC.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Resistive Load (Note 6) R
L 5 kI
Short-Circuit Current V
DD = 5.5V -25 Q6 +25 mA
Power-Up Time From power-down mode 25 Fs
DIGITAL INPUTS (SCLK, DIN, CS, CLR)
Input High Voltage V
IH
0.7 x
V
DD
V
Input Low Voltage V
IL
0.3 x
V
DD
V
Input Leakage Current I
IN VIN = 0V or VDD Q0.1 Q1 FA
Input Capacitance C
IN 10 pF
Hysteresis Voltage V
HYS 0.15 V
DYNAMIC PERFORMANCE (Note 7)
Voltage-Output Slew Rate SR Positive and negative 0.5 V/Fs
Voltage-Output Settling Time 1/4 scale to 3/4 scale, to P 0.5 LSB, 14-bit 18 Fs
Reference -3dB Bandwidth BW
Hex code = 2000 (MAX5214),
Hex code = 8000 (MAX5216)
100 kHz
Digital Feedthrough
Code = 0, all digital inputs from 0V to V
DD,
SCLK < 50MHz
0.5 nV·s
DAC Glitch Impulse Major code transition 2 nV·s
Output Noise
1kHz 73
nV/√Hz
10kHz 70
Integrated Output Noise 0.1Hz to 10Hz 3.5 FV
P-P
POWER REQUIREMENTS
Supply Voltage V
DD 2.7 5.5 V
Supply Current I
DD
No load; all digital inputs at 0V or VDD,
supply current only; excludes reference
input current, midscale
70 80 FA
Power-Down Supply Current PD
IDD No load, all digital inputs at 0V or VDD 0.4 2 FA
TIMING CHARACTERISTICS (Notes 7 and 8) (Figures 1 and 2)
Serial Clock Frequency f
SCLK 0 50 MHz
SCLK Pulse-Width High t
CH 8 ns
SCLK Pulse-Width Low t
CL 8 ns
CS Fall to SCLK Fall Setup Time t
CSS0 8 ns
CS Fall to SCLK Fall Hold Time t
CSH0 0 ns
CS Rise to SCLK Fall Hold Time t
CSH1 0 ns
CS Rise to SCLK Fall t
CSA 12 ns
SCLK Fall to CS Fall t
CSF 100 ns
DIN to SCLK Fall Setup Time t
DS 5 ns
DIN to SCLK Fall Hold Time t
DH 4.5 ns
CS Pulse-Width High t
CSPW 20 ns