Datasheet

MAX5150/MAX5151
Low-Power, Dual, 13-Bit Voltage-Output DACs
with Serial Interface
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ELECTRICAL CHARACTERISTICS—MAX5150 (continued)
(V
DD
= +5V ±10%, V
REFA
= V
REFB
= 2.048V, R
L
= 10kΩ, C
L
= 100pF, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are
at T
A
= +25°C (OS_ tied to AGND for a gain of +2).)
CONDITIONS
Rail-to-rail (Note 2)
To 1/2LSB of full-scale, V
STEP
= 4V
I
SOURCE
= 2mA
UNITS
I
SINK
= 2mA
kΩ24 34R
OS
OSA or OSB Input Resistance
V0 to V
DD
Output Voltage Swing
µs16Output Settling Time
V/µs0.75SRVoltage Output Slew Rate
V
OL
Output Low Voltage V0.13 0.4
MIN TYP MAXSYMBOLPARAMETER
V
OH
Output High Voltage VV
DD -
0.5
µs25Time Required to Exit Shutdown
CS = V
DD
, f
DIN
= 100kHz, V
SCLK
= 5Vp-p
nV-s5Digital Feedthrough
nV-s5Digital Crosstalk
V4.5 5.5V
DD
Positive Supply Voltage
(Note 3) mA0.5 0.65I
DD
Power-Supply Current
(Note 3) µA2 10I
DD (SHDN)
Power-Supply Current
in Shutdown
µA0 ±1Reference Current in Shutdown
ns100t
CP
SCLK Clock Period
ns40t
CH
SCLK Pulse Width High
ns40t
CL
SCLK Pulse Width Low
ns40t
CSS
CS Fall to SCLK Rise
Setup Time
ns0t
CSH
SCLK Rise to CS Rise Hold Time
ns40t
DS
SDI Setup Time
ns0t
DH
SDI Hold Time
C
LOAD
= 200pF ns80t
DO1
SCLK Rise to DOUT
Valid Propagation Delay
Note 1: Accuracy is specified from code 12 to code 8191.
Note 2: Accuracy is better than 1LSB for V
OUT
_ greater than 6mV and less than V
DD
- 50mV. Guaranteed by PSRR test at the end
points.
Note 3: Digital inputs are set to either V
DD
or DGND, code = 0000 hex, R
L
= ∞.
C
LOAD
= 200pF ns80t
DO2
SCLK Fall to DOUT
Valid Propagation Delay
ns40t
CS1
CS Rise to SCLK Rise Hold
ns100t
CSW
CS Pulse Width High
ns10t
CS0
SCLK Rise to CS Fall Delay
DYNAMIC PERFORMANCE
POWER SUPPLIES
DIGITAL OUTPUTS
TIMING CHARACTERISTICS