Datasheet

Detailed Description
The MAX5134–MAX5137 is a family of pin-compatible
and software-compatible 16-bit and 12-bit DACs. The
MAX5134/MAX5135 are low-power, quad 16-/12-bit,
buffered voltage-output, high-linearity DACs. The
MAX5136/MAX5137 are low-power, dual 16-/12-bit,
buffered voltage-output, high-linearity DACs. The
MAX5134–MAX5137 minimize the digital noise
feedthrough from input to output by powering down the
SCLK and DIN input buffers after completion of each 24-
bit serial input. On power-up, the MAX5134–MAX5137
reset the DAC outputs to zero or midscale, depending on
the state of the M/Z input, providing additional safety for
applications that drive valves or other transducers that
need to be off on power-up. The MAX5134–MAX5137
contain a segmented resistor string-type DAC, a serial-in
parallel-out shift register, a DAC register, power-on reset
(POR) circuit, and control logic. On the falling edge of
the clock (SCLK) pulse, the serial input (DIN) data is
shifted into the device, MSB first. During power-down, an
internal 80kΩ resistor pulls DAC outputs to GND.
Output Amplifiers (OUT0–OUT3)
The MAX5134–MAX5137 include internal buffers for all
DAC outputs. The internal buffers provide improved load
regulation and transition glitch suppression for the DAC
outputs. The output buffers slew at 1.25V/µs and drive up
to 2kΩ in parallel with 200pF. The analog supply voltage
(AVDD) determines the maximum output voltage range
of the device as AVDD powers the output buffers.
DAC Reference
Internal Reference
The MAX5134–MAX5137 feature an internal reference
with a nominal output of +2.44V. Connect REFO to REFI
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
Maxim Integrated 9
MAX5134–MAX5137
Pin Description
PIN
MAX5134
MAX5135
MAX5136
MAX5137
TQFN-EP TSSOP TQFN-EP TSSOP
NAME FUNCTION
1 3 1 3 OUT0 Channel 0 Buffered DAC Output
2, 5, 8,
11, 14, 17,
20, 23
—
2, 5, 6, 8,
11, 13, 14,
17, 20, 23
6, 11 N.C. No Connection. Not internally connected.
3 4 3 4 DVDD Digital Power Supply. Bypass DVDD with a 0.1μF capacitor to GND.
4 5 4 5 READY
Active-Low Ready. Indicated configuration ready. Use READY as CS for
consecutive part or as feedback to the μC.
6 6 — — OUT3 Channel 3 Buffered DAC Output
7, 19 7, 15 7, 19 7, 15 GND Ground
9 8 9 8 DIN Data In
10 9 10 9 CS Active-Low Chip-Select Input
12 10 12 10 SCLK Serial-Clock Input
13 11 — — OUT2 Channel 2 Buffered DAC Output
15 12 15 12 LDAC Load DAC Input. Active-low hardware load DAC input.
16 13 16 13 M/Z
Power-Up Reset Select. Connect M/Z to V
AVDD
to power up the DAC
outputs to midscale. Connect M/Z to GND to power up the DAC outputs to
zero.
18 14 18 14 OUT1 Channel 1 Buffered DAC Output
21 16 21 16 REFO Reference Voltage Output
22 1 22 1 REFI
Reference Voltage Input. Bypass REFI with a 0.1μF capacitor to GND
when using external reference.
24 2 24 2 AVDD Analog Power Supply. Bypass AVDD with a 0.1μF capacitor to GND.
— — — — EP
Exposed Pad. Not internally connected. Connect to a ground or leave
unconnected. Not intended as an electrical connection point.