Datasheet

Applications Information
Power-On Reset (POR)
On power-up, the input registers are set to zero, DAC
outputs power up to zero or midscale, depending on
the configuration of M/Z. Connect M/Z to GND to power
the outputs to GND. Connect M/Z to AVDD to power the
outputs to midscale.
To guarantee DAC linearity, wait until the supplies have
settled. Set the LIN bit in the DAC linearity register; wait
10ms, and clear the LIN bit.
Unipolar Output
The MAX5134–MAX5137 unipolar output voltage range
is 0 to V
REFI
. The output buffers each drive a load of
2kΩ in parallel with 200pF.
Bipolar Output
Use the MAX5134–MAX5137 in bipolar applications with
additional external components (see the Typical
Operating Circuit ).
Power Supplies and
Bypassing Considerations
For best performance, use a separate supply for the
MAX5134–MAX5137. Bypass both DVDD and AVDD
with high-quality ceramic capacitors to a low-imped-
ance ground as close as possible to the device.
Minimize lead lengths to reduce lead inductance.
Connect both MAX5134–MAX5137 GND inputs to the
analog ground plane.
Layout Considerations
Digital and AC transient signals on GND inputs can cre-
ate noise at the outputs. Connect both GND inputs to
form the star ground for the DAC system. Refer remote
DAC loads to this system ground for the best possible
performance. Use proper grounding techniques, such
as a multilayer board with a low-inductance ground
plane, or star connect all ground return paths back to
the MAX5134–MAX5137 GND. Carefully lay out the
traces between channels to reduce AC crosscoupling
and crosstalk. Do not use wire-wrapped boards and
sockets. Use shielding to improve noise immunity. Do
not run analog and digital signals parallel to one anoth-
er (especially clock signals) and avoid routing digital
lines underneath the MAX5134–MAX5137 package.
Definitions
Integral Nonlinearity (INL)
INL is the deviation of the measured transfer function
from a best fit straight line drawn between two codes.
For the MAX5134/MAX5136, this best fit line is a line
drawn between codes 3072 and 64,512 of the transfer
function, once offset and gain errors have been nullified.
For the MAX5135/MAX5137, this best fit line is a line
drawn between codes 192 and 4032 of the transfer func-
tion, once offset and gain errors have been nullified.
Differential Nonlinearity (DNL)
DNL is the difference between an actual step height
and the ideal value of 1 LSB. If the magnitude of the
DNL is greater than -1 LSB, the DAC guarantees no
missing codes and is monotonic.
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
14 Maxim Integrated
MAX5134–MAX5137
DAC LATCH CONTENTS
MSB LSB
ANALOG OUTPUT, V
OUT_
1111 1111 1111 1111 V
REF
x (65,535/65,536)
1000 0000 0000 0000 V
REF
x (32,768/65,536) = 1/2 V
REF
0000 0000 0000 0001 V
REF
x (1/65,536)
0000 0000 0000 0000 0
LDAC
OUT_
±2 LSB
t
S
t
LDACPWL
Figure 7. Output Timing
Table 2. MAX5134/MAX5136 Input Code
vs. Output Voltage
DAC LATCH CONTENTS
MSB LSB
ANALOG OUTPUT, V
OUT_
1111 1111 1111 XXXX V
REF
x (4095/4096)
1000 0000 0000 XXXX V
REF
x (2048/4096)
0000 0000 0001 XXXX V
REF
x (1/4096)
0000 0000 0000 XXXX 0
Table 3. MAX5135/MAX5137 Input Code
vs. Output Voltage