Datasheet

Compensation Network
The MAX5096/MAX5097 in LDO mode are compensated
internally with a compensation network around the LDO
error amplifier. When in buck mode, the DC-DC g
M
ampli-
fier must be externally compensated using a network
connected from COMP to ground. The current-mode
control architecture reduces the compensation network
to a single pole-zero. The RC and C network, connected
from the internal transconductance amplifier output to
SGND, can provide a single pole-zero pair. Choose all
the power components like the inductor, output capaci-
tor, and ESR first and design the compensation network
around them. Choose the closed-loop bandwidth (f
C
) to
be approximately 1/10 of the switching frequency. See
the following equations to calculate the compensation
values for the low-ESR output capacitor with ESR zero
frequency, approximately a decade higher than f
C
.
Calculate the dominant pole due to the output capacitor
(C
OUT
) and the load (R
OUT
):
PO
OUT OUT
1
f
2C R
=
×π× ×
where R
OUT
= V
OUT
/I
LOAD
Calculate the R
C
using following equation:
OC
C
MC OUT m ADJ PO
Vf
R
g R gV f
×
=
× ×× ×
where g
MC
is the control to output gain of the MAX5096/
MAX5097 buck converter and is equal to 1.06. V
ADJ
is
the feedback set point equal to 1.237V and g
m
(transcon-
ductance amplifier gain) is equal to 136μS. See Figure 2.
Place a zero (f
Z
) at 0.9 x f
PO
:
C
CFPO PO
1
C
2R f
=
×π× ×
Finally, place a high-frequency pole at the frequency
equal to 1/2 of the converter switching frequency (f
SW
).
P
C SW
1
C
Rf
=
π× ×
Place the compensation network physically close to the
MAX5096/MAX5097.
Switching Between LDO Mode
and Buck Mode
The MAX5096/MAX5097 switch between the buck mode
and LDO mode on the fly. However, care must be taken
to reduce output glitch or overshoot during the switching.
Buck Mode to LDO Mode
The LDO mode is intended for the low 100mA output
current while the buck converter delivers up to 600mA
output current. It is important to first reduce the output
load below 100mA before switching to the LDO mode.
If the output load is higher than 100mA, the MAX5096/
MAX5097 can go into the current limit and the output
drops significantly. Whenever the mode is changed,
output is expected to glitch because the loop dynamics
change due to different error amplifiers when operating in
the LDO and buck modes. The output-voltage undershoot
can be minimized by reducing the output load during
switching and using larger output capacitance.
LDO Mode to Buck Mode
When switching from the LDO mode to buck mode, a
fixed amount of delay (32 cycles) is applied so that the
buck converter control loop and oscillator reach their
steady-state conditions. The 32-cycle delay translates to
approximately 250μs and 100μs for 150kHz and 330kHz
switching frequency versions, respectively. It is recom-
mended that the output load of 600mA must be delayed
by at least this amount of time to allow the MAX5096/
MAX5097 to switch to high-current buck mode. This
ensures that the output does not drop due to the LDO
current-limit protection mechanism.
PCB Layout Guidelines
1) Proper PCB layout is essential. Minimize ground noise
by connecting the anode of the freewheeling rectifier,
the input bypass capacitor ground lead, and the output
filter capacitor ground lead to a large PGND plane.
2) Minimize lead lengths to reduce stray capacitance,
trace resistance, and radiated noise. In particular,
place the Schottky/fast recovery rectifier diode right
next to the device.
MAX5096/MAX5097 40V, 600mA Buck Converters with Low-
Quiescent-Current Linear Regulator Mode
www.maximintegrated.com
Maxim Integrated │ 16