Datasheet

MAX5088/MAX5089
2.2MHz, 2A Buck Converters with an
Integrated High-Side Switch
8 _______________________________________________________________________________________
Pin Description
PIN
NAME
FUNCTION
1, 2
DRAIN
Internal Power MOSFET Drain Connection. Use the MOSFET as a high-side switch and connect DRAIN to the
input supply.
3
COMP
Transconductance Error Amplifier Output. Connect a compensation network from COMP to SGND or from
COMP to FB to SGND (see the Compensation section).
4FBFeedback Input. Connect a resistive divider from the output to FB to SGND to set the output voltage.
5 OSC
Switching Frequency Set Input. Connect a resistor R
OSC
from OSC to SGND to set the switching frequency.
When using external synchronization, program R
OSC
so that (0.2 x f
SYNC
) ≤ f
SW
≤ (1.2 x f
SYNC
). R
OSC
is still
required when external synchronization is used.
6
BYPASS
Reference Bypass Connection. Bypass to SGND with a 0.22µF or greater ceramic capacitor.
7V+
Input Supply Voltage. V+ can range from 5.5V to 23V. Connect V+ and V
L
together for 4.5V to 5.5V input
operation. Bypass V+ to SGND with a minimum of 0.1µF ceramic capacitor.
8V
L
Internal Regulator Output. Bypass V
L
to SGND with a 4.7µF ceramic capacitor and to PGND with a 0.1µF
ceramic capacitor. Connect V+ to V
L
for 4.5V to 5.5V operation.
CKO
Clock Output (MAX5088 Only). CKO is an output with the same frequency as the converter’s switching
frequency and 115° out-of-phase. CKO is used to synchronize the MAX5088 to other MAX5088/MAX5089s.
9
DL
Low-Side Synchronous Rectifier Driver (MAX5089 Only). DL sources 0.7A and sinks 1A to quickly turn on and
off the external synchronous rectifier MOSFET.
10
SGND
Signal Ground
11
PGND
Power Ground. Connect the rectifier diode’s anode, the input capacitor negative terminal, the output capacitor
negative terminal, and V
L
bypass capacitor negative terminal to PGND.
12
SOURCE
Internal Power MOSFET Source Connection. Connect SOURCE to the switched side of the inductor as shown in
Figure 5.
13 SYNC
External Synchronization Input. Connect SYNC to an external logic-level clock to synchronize the MAX5088/
MAX5089. Connect SYNC to SGND when not used.
RESET
Open-Drain Active-Low Reset Output (MAX5088 Only). RESET remains low while the converter’s output is
below 92.5% of V
OUT
’s nominal set point. When V
OUT
rises above 92.5% of its nominal set point, RESET goes
high after the reset timeout period of 200ms (typ).
14
PGOOD
Open-Drain Power-Good Output (MAX5089 Only). PGOOD remains low while the output is below 92.5% of its
nominal set point.
15
BST/VDD
Internal MOSFET Driver Supply Input. Connect BST/VDD to an external ceramic capacitor and diode (see
Figure 5).
16 EN
Enable Input. A logic-low turns off the converter. A logic-high turns on the device. Connect EN to V
L
for an
always-on application.
—EPExposed Pad. Connect to SGND. Solder EP to SGND to enhance thermal dissipation.