Datasheet

The input ripple comprises mainly of ∆V
Q
(caused by the
capacitor discharge) and ∆V
ESR
(caused by the ESR of
the input capacitor). The total voltage ripple is the sum of
∆V
Q
and ∆V
ESR
. Assume the input voltage ripple from
the ESR and the capacitor discharge is equal to 50%
each. The following equations show the ESR and capaci-
tor requirement for a target voltage ripple at the input:
where
where I
OUT
is the output current, D is the duty cycle,
and f
SW
is the switching frequency. Use additional
input capacitance at lower input voltages to avoid pos-
sible undershoot below the UVLO threshold during
transient loading.
Output Capacitors
The allowable output voltage ripple and the maximum
deviation of the output voltage during step load cur-
rents determine the output capacitance and its ESR.
The output ripple comprises of ∆V
Q
(caused by the
capacitor discharge) and ∆V
ESR
(caused by the ESR of
the output capacitor). Use low-ESR ceramic or alu-
minum electrolytic capacitors at the output. For alu-
minum electrolytic capacitors, the entire output ripple is
contributed by ∆V
ESR
. Use the ESR
OUT
equation to cal-
culate the ESR requirement and choose the capacitor
accordingly. If using ceramic capacitors, assume the
contribution to the output ripple voltage from the ESR
and the capacitor discharge to be equal. The following
equations show the output capacitance and ESR
requirement for a specified output voltage ripple.
where:
∆I
P-P
is the peak-to-peak inductor current as calculated
above and f
SW
is the individual converter’s switching
frequency.
The allowable deviation of the output voltage during
fast transient loads also determines the output capaci-
tance and its ESR. The output capacitor supplies the
step load current until the controller responds with a
greater duty cycle. The response time (t
RESPONSE
)
depends on the closed-loop bandwidth of the convert-
er. The high switching frequency of MAX5088/
MAX5089 allows for a higher closed-loop bandwidth,
thus reducing t
RESPONSE
and the output capacitance
requirement. The resistive drop across the output
capacitor’s ESR and the capacitor discharge causes a
voltage droop during a step load. Use a combination of
low-ESR tantalum and ceramic capacitors for better
transient load and ripple/noise performance. Keep the
maximum output voltage deviation below the tolerable
limits of the electronics being powered. When using a
ceramic capacitor, assume an 80% and 20% contribu-
tion from the output capacitance discharge and the
ESR drop, respectively. Use the following equations to
calculate the required ESR and capacitance value:
where I
STEP
is the load step and t
RESPONSE
is the
response time of the controller. The controller response
time depends on the control-loop bandwidth.
Power Dissipation
The MAX5088/MAX5089 are available in thermally
enhanced 16-pin, 5mm x 5mm TQFN packages that
dissipate up to 2.7W at T
A
= +70°C. When the die tem-
perature reaches +170°C, the MAX5088/MAX5089 shut
down (see the Thermal-Overload Protection section).
The power dissipated in the device is the sum of the
power dissipated from supply current (P
Q
), power dis-
sipated due to switching the internal power MOSFET
(P
SW
), and the power dissipated due to the RMS cur-
ESR
V
I
C
It
V
OUT
ESR
STEP
OUT
STEP RESPONSE
Q
=
=
×
∆
∆
∆
∆∆
I
VV V
Vf L
VVV
PP
IN OUT OUT
IN SW
OUT RIPPLE ESR Q
−
=
−
()
×
××
≅+
_
ESR
V
I
C
I
8Vf
ESR
P-P
OUT
P-P
QSW
=
=
××
∆
∆
∆
∆
∆I
VV V
Vf L
and
D
V
V
PP
IN OUT OUT
IN SW
OUT
IN
−
=
−
()
×
××
=
ESR
V
I
I
C
IDD
Vf
ESR
OUT
PP
IN
OUT
QSW
=
+






=
×−
()
×
−
∆
∆
∆
2
1
MAX5088/MAX5089
2.2MHz, 2A Buck Converters with an
Integrated High-Side Switch
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