Datasheet

MAX5088/MAX5089
Enable
EN is an active-high input that turns the MAX5088/
MAX5089 on and off. EN is a TTL logic input with 2.0V
and 0.8V logic-high and low levels, respectively. When
EN is asserted high, the internal digital soft-start cycle
slowly ramps up the internal reference and provides a
soft-start at the output. This hysteresis provides immuni-
ty to the glitches during logic turn-on of the converter.
Voltage variation at EN can interrupt the soft-start
sequence and can cause a latch-up. Ensure that EN
remains high for at least 5ms once it is asserted. Force
EN low to turn off the internal power MOSFET and cause
RESET to pull low (MAX5088) or cause PGOOD to pull
low (MAX5089). Connect EN to V
L
when not used.
Soft-Start/Soft-Stop
The MAX5088/MAX5089 include undervoltage lockout
(UVLO) with hysteresis to prevent chattering during
startup. The UVLO circuit holds the MAX5088/MAX5089
off until V+ reaches 4.5V and turns the devices off
when V+ falls below 4.3V. The MAX5088/MAX5089 also
offer a soft-start feature, which reduces surge currents
and glitches on the input during turn-on. During turn-on
when the UVLO threshold is reached or EN goes from
low to high, the digital soft-start ramps up the reference
(V
BYPASS
) in 64 steps. During a turn-off (by pulling EN
or V+ low), the reference is reduced to zero slowly. The
soft-start and soft-stop periods (t
SS
) are 4096 cycles of
the internal oscillator. To calculate the soft-start/soft-
stop period use the following equation:
f
SW
is the switching frequency of the converter.
Oscillator/Synchronization
(SYNC)/Clock Output (CLKOUT)
The clock frequency (or switching frequency) is gener-
ated internally and is adjustable through an external
resistor connected from OSC to SGND. The relationship
between R
OSC
and f
SW
is:
The adjustment range for f
SW
is from 200kHz to
2.2MHz.
Connect a logic-level clock between 200kHz to 2.2MHz
at SYNC to externally synchronize the MAX5088/
MAX5089’s oscillator (see Figure 7). The MAX5088/
MAX5089 synchronize to the rising edge of the SYNC
clock. The rising edge of the SYNC clock corresponds to
the turn-on edge of the internal n-channel power MOSFET
with a fixed propagation delay. When operating the
MAX5088/MAX5089 with an external SYNC clock, R
OSC
must be installed. Program the internal switching fre-
quency so that (0.2 x f
SYNC
) ≤ f
SW
≤ (1.2 x f
SYNC
). The
minimum pulse width for f
SYNC
is 100ns. Connect SYNC
to SGND if synchronization is not used.
The CKO output (MAX5088 only) is a logic-level clock
with the same frequency as f
SW
and with 115° phase
shift with respect to SYNC clock. Two MAX5088s can
be connected in a master/slave configuration for two-
phase (180°) interleaved operation. The CKO output of
the master drives the SYNC input of the slave to form a
dual-phase converter. To achieve the 180° out-of-phase
operation, program the internal switching frequency of
both converters close to each other by using the same
R
OSC
value. When synchronizing the master-slave con-
figuration using external clock, program the internal
switching frequency using R
OSC
close to the external
clock frequency (f
SYNC
) for 180° ripple phase operation
(see Figure 7). Any difference in the internal switching
frequency and f
SYNC
changes the phase delay. If both
master and slave converters use the same power
source, and share input bypass capacitors, the effec-
tive switching frequency at the input is twice the switch-
ing frequency of the individual converter. Higher ripple
frequency at the input capacitor means a lower RMS
ripple current into the capacitor.
Current Limit
The MAX5088/MAX5089 protect against output over-
load and short-circuit conditions when operated in a
buck configuration. An internal current-sensing stage
develops a voltage proportional to the instantaneous
switch current. When the switch current reaches 2.8A
(typ) the power MOSFET turns off and remains off until
the next on cycle.
During a severe overload or short-circuit condition when
the output voltage is pulled to ground the discharging
slope of the inductor is V
DS
(the voltage across the syn-
chronous FET), or V
F
(the voltage across the rectifying
diode) divided by L. The short off-time does not allow
the current to properly ramp down in the inductor, caus-
ing a dangerous current runaway and possibly destruc-
tion of the device. To prevent this, the MAX5088/
MAX5089 include a frequency foldback feature. When
the current limit is detected the frequency is reduced to
1/4th of the programmed switching frequency. When the
output voltage falls below 1/3rd of its nominal set point
(V
FB
= 0.2V) the converter is turned off and soft-start
cycle is initiated. This reduces the RMS current sourced
by the converter during the fault condition.
R
s
f
OSC
SW
=
×125 10
8
Ω /
t
f
SS
SW
=
4096
2.2MHz, 2A Buck Converters with an
Integrated High-Side Switch
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