Datasheet

MAX5069
High-Frequency, Current-Mode PWM Controller
with Accurate Oscillator and Dual FET Drivers
8 _______________________________________________________________________________________
Pin Description
PIN
MAX5069A
MAX5069D
MAX5069B
MAX5069C
NAME FUNCTION
11RT
Oscillator-Timing Resistor. Connect a resistor from RT to AGND to set the internal oscillator
frequency.
2 — SYNC External-Clock Sync Input. Connect SYNC to AGND when not using an external clock.
— 2 HYST Hysteresis Input
33
SCOMP
Slope-Compensation Capacitor Connection
44DT
Dead-Time Resistor Connection. Connect a resistor from DT to AGND to program the
output dead time. Connect to REG5 for NDRVA and NDRVB maximum 50% duty cycle.
55
UVLO/EN
Externally Programmable Undervoltage Lockout. UVLO/EN programs the input start
voltage. Connect UVLO/EN to AGND to disable the output.
6 6 FB Error-Amplifier Inverting Input
7 7 COMP Error-Amplifier Output
88
FLTINT
Fault-Integration Input. A capacitor connected to FLTINT charges with an internal 60µA
current source during persistent current-limit faults. Switching terminates when V
FLTINT
is
2.8V. An external resistor connected in parallel discharges the capacitor. Switching
resumes when V
FLTINT
drops to 1.6V.
9 9 CS Current-Sense Resistor Connection
10 10 AGND Analog Ground. Connect to PGND.
11 11 PGND Power Ground. Connect to AGND through a ground plane.
12 12
NDRVB
G ate- D r i ver O utp ut B. C onnect N D RV B to the g ate of the exter nal N - channel FE T.
13 13
NDRVA
Gate-Driver Output A. Connect NDRVA to the gate of the external N-channel FET.
14 14 V
CC
9V Linear-Regulator Output. Decouple V
CC
with a minimum 1µF ceramic capacitor to
AGND; also internally connected to the FET drivers.
15 15 IN
Power-Supply Input. IN provides power for all internal circuitry except the gate driver.
Decouple IN with 0.1µF to AGND (see the Typical Operating Circuit).
16 16 REG5 5V Linear-Regulator Output. Decouple REG5 to AGND with 0.1µF ceramic capacitor.
EP EP PAD Exposed Paddle. Connect to GND.