Datasheet

MAX5060/MAX5061
0.6V to 5.5V Output, Parallelable,
Average-Current-Mode DC-DC Controllers
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Use the following equation to calculate the resistor R
CF
:
C
CF
provides a low-frequency pole while R
CF
provides
a midband zero. Place a zero (f
Z
) to obtain a phase
bump at the crossover frequency. Place a high-fre-
quency pole (f
P
) at least a decade away from the
crossover frequency to reduce the influence of the
switching noise and achieve maximum phase margin.
Use the following equations to calculate C
CF
and C
CFF
:
Power Dissipation
The TQFN-28 and TSSOP-16 are thermally enhanced
packages and can dissipate about 2.7W and 1.7W,
respectively. The high-power packages make the high-
frequency, high-current buck converter possible to
operate from a 12V or 24V bus. Calculate power dissi-
pation in the MAX5060/MAX5061 as a product of the
input voltage and the total V
CC
regulator output current
(I
CC
). I
CC
includes quiescent current (I
Q
) and gate-
drive current (I
DD
):
P
D
= V
IN
x I
CC
I
CC
= I
Q
+ [f
SW
x (Q
G1
+ Q
G2
)]
where Q
G1
and Q
G2
are the total gate charge of the
low-side and high-side external MOSFETs at V
GATE
=
5V, I
Q
is estimated from the Supply Current (I
Q
)
vs. Frequency graph in the Typical Operating
Characteristics, and f
SW
is the switching frequency of
the converter.
Use the following equation to calculate the maximum
power dissipation (P
DMAX
) in the chip at a given ambi-
ent temperature (T
A
) :
MAX5060:
P
DMAX
= 34.5 x (150 - T
A
)..............mW
MAX5061:
P
DMAX
= 21.3 x (150 - T
A
)..............mW
PC Board Layout
Use the following guidelines to layout the switching
voltage regulator.
1) Place the IN, V
CC
, and V
DD
bypass capacitors
close to the MAX5060/MAX5061.
2) Minimize the area and length of the high-current
loops from the input capacitor, upper switching
MOSFET, inductor, and output capacitor back to
the input capacitor negative terminal.
3) Keep short the current loop formed by the lower
switching MOSFET, inductor, and output capacitor.
4) Place the Schottky diodes close to the lower
MOSFETs and on the same side of the PC board.
5) Keep the SGND and PGND isolated and connect
them at one single point close to the negative termi-
nal of the input filter capacitor.
6) Run the current-sense lines CSP and CSN very
close to each other to minimize the loop area.
Similarly, run the remote voltage sense lines
SENSE+ and SENSE- close to each other. Do not
cross these critical signal lines through power cir-
cuitry. Sense the current right at the pads of the
current-sense resistors.
7) Avoid long traces between the V
DD
(MAX5060)/V
CC
(MAX5061) bypass capacitors, driver output of the
MAX5060/MAX5061, MOSFET gates, and PGND.
Minimize the loop formed by the V
CC
bypass
capacitors, bootstrap diode, bootstrap capacitor,
MAX5060/MAX5061, and upper MOSFET gate.
8) Place the bank of output capacitors close to the load.
9) Distribute the power components evenly across the
board for proper heat dissipation.
10) Provide enough copper area at and around the
switching MOSFETs, inductor, and sense resistors
to aid in thermal dissipation.
11) Use 4oz copper to keep the trace inductance and
resistance to a minimum. Thin copper PC boards
can compromise efficiency since high currents are
involved in the application. Also, thicker copper
conducts heat more effectively, thereby reducing
thermal impedance.
C
fR
C
fR
CF
ZCF
CFF
PCF
=
×× ×
=
×× ×
1
2
1
2
π
π
R
fL
VR
CF
SW
OUT S
≤
××
×
10
2