Datasheet

MAX5060/MAX5061
0.6V to 5.5V Output, Parallelable,
Average-Current-Mode DC-DC Controllers
20 ______________________________________________________________________________________
where ∆I
L
= peak-to-peak inductor current. Choose
RC2 = 10Ω, V
CC
= 5.1V, and R
SENSE
is a current-
sense resistor. Note that the current limit of MAX5061 is
reduced by 3mV / R
SENSE
.
The no-load output voltage depends on the R
H
, R
F
,
V
REF
(0.6V) and the fixed DC bias voltage at CSP -
CSN. The following equation assumes a 3mV bias volt-
age at CSP - CSN.
Adaptive Voltage Positioning
Powering new-generation processors requires new
techniques to reduce cost, size, and power dissipation.
Voltage positioning reduces the total number of output
capacitors to meet a given transient response require-
ment. Setting the no-load output voltage slightly higher
than the output voltage during nominally loaded condi-
tions allows a larger downward-voltage excursion when
the output current suddenly increases. Regulating at a
lower output voltage under a heavy load allows a larger
upward-voltage excursion when the output current sud-
denly decreases. Allowing a larger voltage-step excur-
sion reduces the required number of output capacitors
or allows for the use of higher ESR capacitors.
Voltage positioning may require the output to regulate
away from a center value. Define the center value as
the voltage where the output drops (∆V
OUT
/2) at one
half the maximum output current (Figure 7).
Set the voltage-positioning window (∆V
OUT
) using the
resistive feedback of the voltage-error amplifier (VEA).
Use the following equations to calculate the voltage-
positioning window (Figure 5):
MAX5060:
MAX5061:
R
IN
and R
F
are the input and feedback resistors of
VEA. G
C
is the current-loop transconductance and R
S
is the current-sense resistor.
MOSFET Gate Drivers (DH_, DL_)
The high-side (DH) and low-side (DL) drivers drive the
gates of external n-channel MOSFETs (Figures 1 and 2).
The drivers’ 4A peak sink- and source-current capability
provides ample drive for the fast rise and fall times of the
switching MOSFETs. Faster rise and fall times result in
reduced cross-conduction losses. For modern CPU volt-
age-regulating module applications, where the duty
cycle is less than 50%, choose high-side MOSFETs (Q1)
with a moderate R
DS(ON)
and a very low gate charge.
Choose low-side MOSFETs (Q2) with very low R
DS(ON)
and moderate gate charge. Size the high-side and low-
side MOSFETs to handle the peak and RMS currents
during overload conditions.
The driver block also includes a logic circuit that provides
an adaptive nonoverlap time to prevent shoot-through
currents during transition. The typical nonoverlap time is
35ns between the high-side and low-side MOSFETs.
BST
The MAX5060 uses V
DD
to power the low- and high-side
MOSFET drivers. The low- and high-side drivers in the
MAX5061 are powered from V
CC
. The high-side driver
derives its power through a bootstrap capacitor and V
DD
supplies power internally to the low-side driver. Connect a
0.47µF low-ESR ceramic capacitor between BST and LX.
Connect a Schottky rectifier from BST to V
DD
on the
MAX5060, or to V
CC
on the MAX5061. Reduce the PC
board area formed by the boost capacitor and rectifier.
∆V
IxR
GxR
OUT
OUT H
cF
=
∆V
IR
GR
RR
R
G
R
OUT
OUT IN
CF
HL
L
C
S
=
×
×
×
+
=
.0 0289
V
V
R
V
R
RV
OUT NL
REF
L
REF
F
H REF()
[(
.
)]=+
−
×+
01
LOAD (A)
V
CNTR
NO LOAD
1/2 LOAD
FULL LOAD
VOLTAGE-POSITIONING WINDOW
V
CNTR
+
∆V
OUT
/2
V
CNTR
-
∆V
OUT
/2
Figure 7. Defining the Voltage-Positioning Window