Datasheet

MAX5060/MAX5061
0.6V to 5.5V Output, Parallelable,
Average-Current-Mode DC-DC Controllers
14 ______________________________________________________________________________________
Block Diagram
2 x f
S
(V/s)
RAMP
RT/SYNC
CSP
CSN
SGND
SENSE-
SENSE+
CLP
LIM
IN
EN
V
DD
BST
DH
LX
DL
PGND
PGOOD
A
V
= 34.5
A
V
= 4
100kΩ
126.7kΩ
PWM
COMPARATOR
0.5V x V
CC
TO INTERNAL
CIRCUITS
HICCUP MODE
CURRENT LIMIT
S
R
Q
Q
V_IOUT
g
m
= 500µS
DIFF
CLKOUT
CLK
CPWM
CEA
V
CLAMP
HIGH
V
CLAMP
LOW
CA
V
CC
0.1 x V
REF
N
+0.6V
V
REF
= 0.6V
V
CM
(0.6V)
OVP COMP
0.12 x V
REF
LATCH
RAMP
GENERATOR
SOFT-
START
OSCILLATOR
CLEAR ON UVLO RESET OR
ENABLE LOW
OVP LATCH
DIFF
AMP
EAN
EAOUT
OVI
VEA
ERROR AMP
0.5 x V
CLAMP
V
CM
V
CM
I
S
V
CC
C
t
R
T
S
R
Q
Q
UVLO
POR
TEMP SENSOR
5V
LDO
REGULATOR
MAX5060
Figure 3. Functional Diagram (MAX5060)