Datasheet

MAX5038/MAX5041
Dual-Phase, Parallelable, Average Current-Mode
Controllers
______________________________________________________________________________________ 17
Set the voltage-positioning window (∆V
OUT
) using the
resistive feedback of the VEA. Use the following equa-
tions to calculate the voltage-positioning window for the
MAX5038:
Use the following equation to calculate the voltage-posi-
tioning window for the MAX5041:
where R
IN
and R
F
are the input and feedback resistors of
the VEA, G
C
is the current-loop gain and R
S
is the cur-
rent-sense resistor or, if using lossless inductor current
sensing, the DC resistance of the inductor.
Phase-Locked Loop: Operation and
Compensation
The PLL synchronizes the internal oscillator to the
external frequency source when driving CLKIN.
Connecting CLKIN to V
CC
or SGND forces the PWM
frequency to default to the internal oscillator frequency
of 500kHz or 250kHz, respectively. The PLL uses a
conventional architecture consisting of a phase detec-
tor and a charge pump capable of providing 20µA of
output current. Connect an external series combination
capacitor (C25) and resistor (R4) and a parallel capaci-
tor (C26) from PLLCMP to SGND to provide frequency
compensation for the PLL (Figure 1). The pole-zero pair
compensation provides a zero at f
Z
= 1 / [R4 x (C25 +
C26)] and a pole at f
P
= 1 / (R4 x C26). Use the follow-
ing typical values for compensating the PLL:
R4 = 7.5kΩ, C25 = 4.7nF, C26 = 470pF. If changing the
PLL frequency, expect a finite locking time of approxi-
mately 200µs.
The MAX5038/MAX5041 require compensation on
PLLCMP even when operating from the internal oscilla-
tor. The device requires an active PLL in order to gen-
erate the proper internal PWM clocks.
MOSFET Gate Drivers (DH_, DL_)
The high-side (DH_) and low-side (DL_) drivers drive
the gates of external N-channel MOSFETs (Figures 1
and 2). The drivers’ high-peak sink and source current
capability provides ample drive for the fast rise and fall
times of the switching MOSFETs. Faster rise and fall
times result in reduced cross-conduction losses. For
modern CPU voltage-regulating module applications
where the duty cycle is less than 50%, choose high-
side MOSFETs (Q1 and Q3) with a moderate R
DS(ON)
and a very low gate charge. Choose low-side
MOSFETs (Q2 and Q4) with very low R
DS(ON)
and
moderate gate charge.
The driver block also includes a logic circuit that pro-
vides an adaptive non-overlap time to prevent shoot-
through currents during transition. The typical
non-overlap time is 60ns between the high-side and
low-side MOSFETs.
BST_
V
DD
powers the low- and high-side MOSFET drivers.
Connect a 0.47µF low-ESR ceramic capacitor between
BST_ and LX_. Bypass V
CC
to PGND with 4.7µF and
0.1µF low-ESR ceramic capacitors. Reduce the PC
board area formed by these capacitors, the rectifier
diodes between V
CC
and the boost capacitor, the
MAX5038/MAX5041, and the switching MOSFETs.
G
R
C
S
=
005.
∆V
IR
GR
RR
R
OUT
OUT IN
CF
HL
L
=
×
××
()
×
+
2
G
R
C
S
=
005.
∆V
IR
GR
OUT
OUT IN
CF
=
×
××2
LOAD (A)
V
CNTR
NO LOAD
1/2 LOAD
FULL LOAD
VOLTAGE-POSITIONING W
INDOW
V
CNTR
+ ∆V
OUT
/2
V
CNTR
- ∆V
OUT
/2
Figure 5. Defining the Voltage-Positioning Window
(8)
(9)
(10)
(11)