Datasheet

MAX5038/MAX5041
Dual-Phase, Parallelable, Average Current-Mode
Controllers
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The outer voltage control loop consists of the differen-
tial amplifier (DIFF AMP), reference voltage, and VEA.
The unity-gain differential amplifier provides true differ-
ential remote sensing of the output voltage. The differ-
ential amplifier output connects to the inverting input
(EAN) of the VEA. The noninverting input of the VEA is
internally connected to an internal precision reference
voltage. The MAX5041 reference voltage is set to +1.0V
and the MAX5038 reference is set to the preset output
voltage. The VEA controls the two inner current loops
(Figures 3a and 3b). Use a resistive feedback network
to set the VEA gain as required by the adaptive volt-
age-positioning circuit (see the Adaptive Voltage
Positioning section).
Current-Sense Amplifier
The differential current-sense amplifier (CA_) provides a
DC gain of 18. The maximum input offset voltage of the
current-sense amplifier is 1mV and the common-mode
voltage range is -0.3V to +3.6V. The current-sense ampli-
fier senses the voltage across a current-sense resistor.
Peak-Current Comparator
The peak-current comparator provides a path for fast
cycle-by-cycle current limit during extreme fault condi-
tions such as an output inductor malfunction (Figure 4).
Note that the average current-limit threshold of 48mV
still limits the output current during short-circuit condi-
tions. To prevent inductor saturation, select an output
inductor with a saturation current specification greater
than the average current limit (48mV). Proper inductor
selection ensures that only extreme conditions trip the
peak-current comparator, such as a cracked output
inductor. The 112mV voltage threshold for triggering
the peak-current limit is twice the full-scale average
current-limit voltage threshold. The peak-current com-
parator has a delay of only 260ns.
Current-Error Amplifier
Each phase of the MAX5038/MAX5041 has a dedicated
transconductance current-error amplifier (CEA_) with a
typical g
m
of 550µS and 320µA output sink and source
current capability. The current-error amplifier outputs,
CLP1 and CLP2, serve as the inverting input to the
PWM comparator. CLP1 and CLP2 are externally
accessible to provide frequency compensation for the
inner current loops (Figures 3a and 3b). Compensate
CEA_ such that the inductor current down slope, which
becomes the up slope to the inverting input of the PWM
comparator, is less than the slope of the internally gen-
erated voltage ramp (see the Compensation section).
PWM Comparator and R-S Flip-Flop
The PWM comparator (CPWM) sets the duty cycle for
each cycle by comparing the output of the current-error
amplifier to a 2V
P-P
ramp. At the start of each clock
cycle, an R-S flip-flop resets and the high-side driver
(DH_) turns on. The comparator sets the flip-flop as
soon as the ramp voltage exceeds the CLP_ voltage,
thus terminating the ON cycle (Figure 4).
2 x f
s
(V/s)
RAMP
CLK
CSP_
CSN_
GM
IN
SHDN
CLP_
DRV_V
CC
BST_
DH_
LX_
DL_
PGND
A
V
= 18
PWM
COMPARATOR
PEAK-CURRENT
COMPARATOR
112mV
S
R
Q
Q
G
m
=
500µS
Figure 4. Phase Circuit (Phase 1/Phase 2)