Datasheet
Ensure that the ripple specification of the input capacitor
exceeds the worst-case capacitor RMS ripple current.
Use the following equations to calculate the input capaci-
tor RMS current:
22
CRMS PRMS AVGIN
I I I= −
where :
( )
(
)
22
PRMS PK DC PK DC
OUT OUT
AVGIN
IN
LL
PK OUT DC OUT
OUT
IN
D
I I I I I
3
VI
I
V
II
I I , I I
22
V
and D
V
= + +× ×
×
=
×η
∆∆
=+=−
=
I
PRMS
is the input switch RMS current, I
AVGIN
is the input
average current, and η is the converter efficiency.
The ESR of aluminum electrolytic capacitors increases
significantly at cold temperatures. Use a 1μF or greater
value ceramic capacitor in parallel with the aluminum
electrolytic input capacitor, especially for input voltages
below 8V.
Output Filter Capacitor
The worst-case peak-to-peak and RMS capacitor ripple
current, allowable peak-to-peak output ripple voltage, and
the maximum deviation of the output voltage during load
steps determine the capacitance and the ESR require-
ments for the output capacitors.
The output capacitance and its ESR form a zero, which
improves the closed-loop stability of the buck regulator.
Choose the output capacitor so the ESR zero frequency
(f
Z
) occurs between 20kHz to 40kHz. Use the following
equation to verify the value of f
Z
. Capacitors with 100mΩ
to 250mΩ ESR are recommended to ensure the closed-
loop stability while keeping the output ripple low.
Z
OUT OUT
1
f
2 C ESR
=
×π× ×
The output ripple is comprised of ΔV
OQ
(caused by the
capacitor discharge) and ΔV
OESR
(caused by the ESR
of the capacitor). Use low-ESR tantalum or aluminum
electrolytic capacitors at the output. Assuming that the
contributions from the ESR and capacitor discharge equal
80% and 20%, respectively, calculate the output capaci-
tance and the ESR required for a specified ripple using
the following equations:
OESR
OUT
L
L
OUT
OQ SW
V
ESR
I
I
C
2.2 V f
∆
=
∆
∆
≈
×∆ ×
The MAX5033 has an internal soft-start time (t
SS
) of
400μs. It is important to keep the output rise time at
startup below t
SS
to avoid output overshoot. The output
rise time is directly proportional to the output capacitor.
Use 68μF or lower capacitance at the output to control the
overshoot below 5%.
In a dynamic load application, the allowable deviation of
the output voltage during the fast-transient load dictates
the output capacitance value and the ESR. The output
capacitors supply the step load current until the controller
responds with a greater duty cycle. The response time
(t
RESPONSE
) depends on the closedloop bandwidth of
the converter. The resistive drop across the capacitor
ESR and capacitor discharge cause a voltage droop dur-
ing a step load. Use a combination of low-ESR tantalum
and ceramic capacitors for better transient load and
ripple/noise performance. Keep the maximum output-
voltage deviation above the tolerable limits of the elec-
tronics being powered. Assuming a 50% contribution from
the output capacitance discharge and the ESR drop, use
the following equations to calculate the required ESR and
capacitance value:
OESR
OUT
STEP
STEP RESPONSE
OUT
OQ
V
ESR
I
It
C
V
∆
=
×
=
∆
where I
STEP
is the load step and t
RESPONSE
is the
response time of the controller. Controller response time
is approximately one-third of the reciprocal of the closed-
loop unity-gain bandwidth, 20kHz (typ).
PCB Layout Considerations
Proper PCB layout is essential. Minimize ground noise
by connecting the anode of the Schottky rectifier, the
input bypass-capacitor ground lead, and the output
filter-capacitor ground lead to a single point (star-ground
configuration). A ground plane is required. Minimize lead
lengths to reduce stray capacitance, trace resistance, and
radiated noise. In particular, place the Schottky rectifier
diode right next to the device. Also, place BST and VD
bypass capacitors very close to the device. Use the PCB
copper plane connecting to V
IN
and LX for heatsinking.
MAX5033 500mA, 76V, High-Efciency, MAXPower
Step-Down DC-DC Converter
www.maximintegrated.com
Maxim Integrated
│
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