Datasheet

SAS/SATA Single Lane 2:1/1:2 Multiplexer/
Demultiplexer Plus Redriver with Equalization
MAX4986
12
Applications Information
Layout
Circuit board layout and design can significantly affect
the performance of the MAX4986. Use good, high-fre-
quency design techniques, including minimizing ground
inductance and using controlled impedance transmis-
sion lines on data signals. It is recommended to place
1FF and 0.01FF power-supply bypass capacitors in
parallel as close to V
CC
as possible for each V
CC
pin.
Always connect V
CC
to a power plane.
Exposed-Pad Package
The exposed-pad, 42-pin TQFN package incorporates
features that provide a very low-thermal resistance
path for heat removal from the IC. The exposed pad
on the MAX4986 must be soldered to the circuit board
ground plane for proper thermal performance. For
more information on exposed-pad packages, refer
to Maxim Application Note 862: HFAN-08.1: Thermal
Considerations of QFN and Other Exposed-Paddle
Packages.
Typical Application Circuits
MAX4986
INA
INB
OUTB
OUTA
NOTE: TWO HOSTS SHARING A SINGLE SAS DRIVE WITH CABLE-DETECT.
GPIO
MIDPLANE (FR4)
MAIN BOARD
SAS
DRIVE
Rx
Tx
HOST AHOST B
Rx
Tx
SEL1
SEL2
IN
EN
OUT
CONNECTOR CONNECTOR
MAX4986
IN
OUT
NOTE: SINGLE HOST WITH TWO SAS DRIVES AND CABLE-DETECT.
MIDPLANE (FR4)
MAIN BOARD
SAS
DRIVE A
SAS
DRIVE B
Tx
HOST
Rx
INB
OUTA
OUTB
INA
GPIO
SEL1
SEL2
EN
CONNECTOR
CONNECTORCONNECTOR