Datasheet

MAX4968/MAX4968A
16-Channel, Linear, High-Voltage
Analog Switches
6
Figure 2. Serial Interface Timing
Figure 3. Latch-Enable Interface Timing
Test Circuits/Timing Diagrams (continued)
DIN D
N+1
D
N-1
D
N
50%
50% 50%
50%
50%50%
50%
90%
10%
50%
t
CS
t
WL
t
DS
t
DH
t
DO
t
OFF
t
WC
t
ON
50%
LE
CLK
DOUT
OFF
ON
SWITCH
CLR
DIN
DATA FROM PREVIOUS DATA BYTE
POWER-UP DEFAULT: D[15:0] = 0
D15
D15
D14
D13
D14
D13
D1 D0
D1 D0
D15
LSB
MSB
LE
CLK
DOUT