Datasheet

MAX4950
Quad PCI Express Equalizer/Redriver
4 _______________________________________________________________________________________
Note 3: All devices are 100% production tested at T
A
= +70°C. Specifications for all temperature limits are guaranteed by design.
Note 4: Currents are applicable for both PCIe Generation I and Generation II speeds. Power-saving mode (P_SAV), where electrical
idle and receiver detection are only performed on channel 0 and reduced output swing (O_AMP) reduces this current. Table
5 summarizes the predicted power consumption.
Note 5: Guaranteed by design, unless otherwise noted.
Note 6: Equivalent to same amount of deemphasis driving the input.
Note 7: Rise and fall times are measured using 20% and 80% levels.
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +3.0V to +3.6V, C
CL
= 75nF coupling capacitor on each output, R
L
= 50Ω resistor on each output, T
A
= 0°C to +70°C, unless
otherwise noted. Typical values are at V
CC
= +3.3V and T
A
= +25°C.) (Note 3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Electrical Idle Detect
Threshold
V
TX-IDLE-
THRESH
Squarewave input at 500MHz 65 85 120 mV
P-P
Output Voltage During
Electrical Idle (AC)
V
TX-IDLE-DIFF-
AC-P
|(V
OUT_P
- V
OUT_N
)|, f = 2.5GHz 20 mV
P-P
Receiver Detect Pulse
Amplitude
V
TX-RCV-
DETECT
Voltage change in positive direction 600 mV
Receiver Detect Pulse Width 100 ns
Receiver Detect Retry Period 200 ns
CONTROL LOGIC (INEQ1, INEQ0, OEQ1, OEQ0, EN, RX_DET, O_AMP, P_SAV)
Input Logic-Level Low V
IL
0.6 V
Input Logic-Level High V
IH
1.4 V
Input Logic Hysteresis V
HYST
130 mV
Input Leakage Current I
IN
V
CONTROL_LOGIC
= +0.5V or +1.5V -50 +50 µA
ESD PROTECTION
All Pins Human Body Model (HBM) ±2 kV
DE dB
V
V
HIGH P P
LOW P P
() log
_
_
=
⎛
⎝
⎜
⎞
⎠
⎟
⎡
⎣
⎢
⎢
⎤
⎦
−
−
20
⎥⎥
⎥
Timing Diagram
V
LOW_P-P
V
HIGH_P-P
Figure 1. Illustration of Output Deemphasis