Datasheet

Dual/Quad, Unipolar/Bipolar,
High-Voltage Digital Pulsers
MAX4940/MAX4940A
8 ______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1 INP1A Channel 1A High-Side Logic Input. See the Truth Tables section.
2 CLP1A
Channel 1A Clamp Logic Input. Clamp is turned on when CLP1A is high and when INP1A and
INN1A are low. See the Truth Table section.
3 INN1A Channel 1A Low-Side Logic Input. See the Truth Tables section.
4 INP2A Channel 2A High-Side Logic Input. See the Truth Tables section.
5 CLP2A
Channel 2A Clamp Logic Input. Clamp is turned on when CLP2A is high and when INP2A and
INN2A are low. See the Truth Tables section.
6 INN2A Channel 2A Low-Side Logic Input. See the Truth Tables section.
7 AGND Analog Ground. Must be connected to common GND.
8 EN Enable Logic Input. Drive EN high to enable OUT1A, OUT1B, OUT2A, and OUT2B.
9 INP2B Channel 2B High-Side Logic Input. See the Truth Tables section.
10 CLP2B
Channel 2B Clamp Logic Input. Clamp is turned on when CLP2B is high and when INP2B and
INN2B are low. See the Truth Tables section.
11 INN2B Channel 2B Low-Side Logic Input. See the Truth Tables section.
12 INP1B Channel 1B High-Side Logic Input. See the Truth Tables section.
13 CLP1B
Channel 1B Clamp Logic Input. Clamp is turned on when CLP1B is high and when INP1B and
INN1B are low. See the Truth Tables section.
14 INN1B Channel 1B Low-Side Logic Input. See the Truth Tables section.
15 V
EE
Negative Supply Input. Gate-drive supply voltage for the clamp. Bypass V
EE
to GND with a 0.1FF
capacitor as close as possible to the device.
16, 27, 29,
34, 37, 42,
44, 55
GND Ground
17, 54 V
CC
Gate-Drive Supply Voltage Input. Bypass V
CC
to GND with a 0.1FF capacitor as close as possible
to the device.
18 C
DP1B
Channel 1B High-Side Driver Output. Connect a 3.3nF capacitor between C
DP1B
and C
GP1B
as
close as possible to the device
.
19 C
DN1B
Channel 1B Low-Side Driver Output. Connect a 3.3nF capacitor between C
DN1B
and C
GN1B
as
close as possible to the device
.
20 C
DN2B
Channel 2B Low-Side Driver Output. Connect a 3.3nF capacitor between C
DN2B
and C
GN2B
as
close as possible to the device
.
21 C
DP2B
Channel 2B High-Side Driver Output. Connect a 3.3nF capacitor between C
DP2B
and C
GP2B
as
close as possible to the device
.
22 C
GP2B
Channel 2B High-Side Gate Input. Connect a 3.3nF capacitor between C
DP2B
and C
GP2B
as close
as possible to the device
.
23 C
GN2B
Channel 2B Low-Side Gate Input. Connect a 3.3nF capacitor between C
DN2B
and C
GN2B
as close
as possible to the device
.
24 C
GN1B
Channel 1B Low-Side Gate Input. Connect a 3.3nF capacitor between C
DN1B
and C
GN1B
as close
as possible to the device
.
25 C
GP1B
Channel 1B High-Side Gate Input. Connect a 3.3nF capacitor between C
DP1B
and C
GP1B
as close
as possible to the device
.