Datasheet

14 _____________________________________________________________________________________

MAX4936–MAX4939

Octal High-Voltage Transmit/Receive Switches

Latch Clear (CLR)

Drive CLR logic-high to reset the contents of the latch to

zero and open all T/R switches. CLR does not affect the

contents of the shift register. Once CLR is high again,

and LE is driven low, the contents of the shift register are

loaded into the latch.

Power-On Reset

The devices feature a power-on-reset circuit to ensure

all switches are off at power-on. The internal 12-bit serial

shift register and latch are set to zero on power-up.

Figure 4. Latch-Enable Interface Timing

Figure 3. Diode Bias Current Control

CLK

DOUT

D11'–D0' FROM PREVIOUS DATA

POWER-UP DEFAULT: D11–D0 = 0

DIN

D11

MSB

LSB

D10

D11'

D10'

D9'

D0'

D1'

D11

LVCC (LVEE)

DIODE BRIDGE