Datasheet
MAX4928A/MAX4928B
DisplayPort/PCIe Passive Switches
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Detailed Description
The MAX4928A/MAX4928B high-speed passive switches
route PCI Express (PCIe) data and/or DisplayPort signals
between two possible destinations. The MAX4928A/
MAX4928B are ideal for routing signals between a graph-
ics memory controller hub (GMCH) and either a
DisplayPort or PCIe connector.
The MAX4928A/MAX4928B feature a single digital con-
trol input (SEL) to switch signal paths and a latch input
(LE) that holds the switches in a given state.
Digital Control Input (SEL)
The MAX4928A/MAX4928B provide a single digital con-
trol input (SEL) to select the signal path between the
IN_ and D_/TX_, X_ and HPD_/RX1_, and OUT_ and
AUX_/RX0_ channels. The truth tables for the
MAX4928A/MAX4928B are depicted in the
Functional
Diagrams/Truth Table
. Drive SEL rail-to-rail to minimize
power consumption.
Latch Control Input (LE)
The MAX4928A/MAX4928B provide a single digital con-
trol input (LE) to latch the signal paths between the IN_
and D_/TX_, X_ and HPD_/RX1_, and OUT_ and
AUX_/RX0_ channels. When LE is driven high, the
switches are held in their previous state, regardless of
the input signal to SEL. Drive LE rail-to-rail to minimize
power consumption.
Analog Signal Levels
The MAX4928A/MAX4928B accept standard PCIe sig-
nals to a maximum of (V
DD
- 1.8V). Signals on the IN_+
channels are routed to either the D_+ or TX_+ channels,
signals on the X+ channel are routed to either HPD1 or
RX1+ channels, and signals on the OUT+ channel are
routed to either AUX+ or RX0+ channels. Signals on the
IN_- channels are routed to either the D_- or TX_- chan-
nels, signals on the X- channel are routed to either HPD2
or RX1- channels, and signals on the OUT- channel are
routed to either AUX- or RX0- channels. The
MAX4928A/MAX4928B are bidirectional switches, allow-
ing IN_, X_, OUT_, D_, TX_, HPD_, RX_, and AUX_ to be
used as either inputs or outputs.
Applications Information
DisplayPort/PCIe Switching
The MAX4928A/MAX4928B primary applications are
aimed to switch between a GMCH and either a
DisplayPort or PCIe connector. The MAX4928A/
MAX4928B contain n-channel switches to permit differ-
ential signals to be selected between a PCIe Gen II
socket or to a DisplayPort connector. Each device han-
dles up to six pairs of signals. The DisplayPort signal is
an AC-coupled 8b/10b encoded differential signal
ranging up to 2.7 Gbps. The PCIe Gen I and Gen II sig-
nals are AC-coupled, 8b/10b encoded differential sig-
nals ranging up to 5.0Gbps.
Board Layout
High-speed switches require proper layout and design
procedures for optimum performance. Keep design-
controlled impedance PCB traces as short as possible
or follow impedance layouts per the PCIe specification.
Ensure that power-supply bypass capacitors are
placed as close as possible to the device. Multiple
bypass capacitors are recommended. Connect all
grounds and the exposed pad to large ground planes.
Chip Information
PROCESS: CMOS
Pin Description (continued)
PIN
MAX4928A MAX4928B
NAME FUNCTION
47 39 TX2+ Analog Switch 3—Normally Closed Positive Terminal
51 40 TX1- Analog Switch 2—Normally Closed Negative Terminal
52 41 TX1+ Analog Switch 2—Normally Closed Positive Terminal
53 42 TX0- Analog Switch 1—Normally Closed Negative Terminal
54 43 TX0+ Analog Switch 1—Normally Closed Positive Terminal
— — EP Exposed Pad. Connect EP to GND. Exposed pad internally connected to GND.