Datasheet

MAX4850/MAX4850H/MAX4852/MAX4852H
Dual SPDT Analog Switches with
Over-Rail Signal Handling
12 ______________________________________________________________________________________
Test Circuits/Timing Diagrams
t
R
< 20ns
t
F
< 20ns
50%
LOGIC
INPUT
R
L
COM_
GND
IN_
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
V
OUT
= V
NO (
R
L
)
R
L
+ R
ON
V
NO
t
OFF
0V
NO_
0.9 x V
0UT
0.9 x V
OUT
t
ON
V
OUT
SWITCH
OUTPUT
LOGIC
INPUT
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
V
CC
C
L
V
CC
V
OUT
MAX4850_
MAX4852_
V
CC
0V
SWITCH
INPUT
NORMAL MODE NORMAL MODE
HIGH-Z MODE
V
CC
+ 0.5V
t
HIZ
t
HIZB
Figure 1. Switching Time
t
skew_i
90%
50%
10%
90%
50%
10%
t
fi
INPUT A
INPUT A-
t
ri
t
skew_o
90%
50%
10%
90%
50%
10%
t
fo
OUTPUT B
OUTPUT B-
t
ro
B-
C
L
A-
R
s
A
B
C
L
TxD+
TxD-
R
s
R
s
= 39Ω
C
L
= 50pF
DELAY DUE TO SWITCH FOR RISING INPUT AND RISING OUTPUT SIGNALS.
DELAY DUE TO SWITCH FOR FALLING INPUT AND FALLING OUTPUT SIGNALS.
CHANGE IN SKEW THROUGH THE SWITCH FOR OUTPUT SIGNALS.
CHANGE IN SKEW THROUGH THE SWITCH FOR INPUT SIGNALS.
|t
skew_i
|
|t
skew_o
|
|t
fo -
t
fi
|
|t
ro -
t
ri
|
Figure 2. Input/Output Skew Timing Diagram