Datasheet

MAX4762–MAX4764/MAX4764A/MAX4765
Low-Voltage, Dual SPDT, Audio Clickless
Switches with Negative Rail Capability
_______________________________________________________________________________________ 9
Test Circuits/Timing Diagrams
t
r
< 5ns
t
f
< 5ns
50%
0V
LOGIC
INPUT
R
L
COM_
GND
IN_
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
V
OUT
= V
N_ (
R
L
)
R
L
+ R
ON
V
N_
V
CC
t
OFF
0V
NO_
OR NC_
0.9 x V
0UT
0.9 x V
OUT
t
ON
V
OUT
SWITCH
OUTPUT
LOGIC
INPUT
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
V
CC
C
L
V
CC
V
OUT
MAX4762–MAX4764
MAX4764A/MAX4765
Figure 2. Switching Time
GND
NC_
OR NO_
C
L
V
OUT
V
CC
V
OUT
IN
OFF
ON
OFF
∆V
OUT
Q = (∆V
OUT
)(C
L
)
COM_
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
OFF
ON
OFF
IN
V
IL
TO V
IH
V
CC
IN_
MAX4762–MAX4764
MAX4764A/MAX4765
Figure 4. Charge Injection
50%
V
CC
0V
LOGIC
INPUT
V
OUT
0.9 x V
OUT
t
BBM
LOGIC
INPUT
R
L
GND
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
NO_
IN_
NC_
V
OUT
V
CC
V
CC
C
L
V
N_
COM_
MAX4762–MAX4764
MAX4764A/MAX4765
Figure 3. Break-Before-Make Interval