Datasheet

MAX4760/MAX4760A/MAX4761/MAX4761A
High-Bandwidth, Quad DPDT Switches
_______________________________________________________________________________________ 9
Timing Circuits/Timing Diagrams
t
r
< 5ns
t
f
< 5ns
50%
0V
LOGIC
INPUT
R
L
COM_
GND
IN_
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
V
OUT
= V
N_ (
R
L
)
R
L
+ R
ON
V
N_
V+
t
OFF
0V
NO_
OR NC_
0.9 x V
0UT
0.9 x V
OUT
t
ON
V
OUT
SWITCH
OUTPUT
LOGIC
INPUT
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
V+
C
L
V+
V
OUT
50%
MAX4760/MAX4760A
MAX4761/MAX4761A
Figure 2. Switching Time
50%
V+
0V
LOGIC
INPUT
V
OUT
0.9 x V
OUT
t
BBM
LOGIC
INPUT
R
L
GND
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
NO_
IN_
NC_
V
OUT
V+
V+
C
L
V
N_
COM_
MAX4760/MAX4760A
MAX4761/MAX4761A
Figure 3. Break-Before-Make Interval