Datasheet

MAX4760/MAX4760A/MAX4761/MAX4761A
High-Bandwidth, Quad DPDT Switches
10 ______________________________________________________________________________________
Timing Circuits/Timing Diagrams (continued)
t
skew_i
90%
50%
10%
90%
50%
10%
t
fi
INPUT A
INPUT A-
t
ri
t
skew_o
90%
50%
10%
90%
50%
10%
t
fo
OUTPUT B
OUTPUT B-
t
ro
C
L
A-
A+
R
s
B+
B-
C
L
TxD+
TxD-
R
s
R
s
= 39Ω
C
L
= 50pF
DELAY DUE TO SWITCH FOR RISING INPUT AND RISING OUTPUT SIGNALS.
DELAY DUE TO SWITCH FOR FALLING INPUT AND FALLING OUTPUT SIGNALS.
CHANGE IN SKEW THROUGH THE SWITCH FOR OUTPUT SIGNALS.
CHANGE IN SKEW THROUGH THE SWITCH FOR INPUT SIGNALS.
|t
skew_i
|
|t
skew_o
|
|t
fo -
t
fi
|
|t
ro -
t
ri
|
MAX4760/MAX4760A
MAX4761/MAX4761A
Figure 4. Input/Output Skew Timing Diagram
V
GEN
GND
COM_
C
L
V
OUT
V+
V
OUT
IN
OFF
ON
OFF
ΔV
OUT
Q = (ΔV
OUT
)(C
L
)
NC_
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
OFF
ON
OFF
IN
V
IL
TO V
IH
V+
R
GEN
IN_
OR NO_
MAX4760/MAX4760A
MAX4761/MAX4761A
Figure 5. Charge Injection