Datasheet

MAX4754/MAX4754A/MAX4755/MAX4756/MAX4756A
0.5 Ω , Quad SPDT Switches in UCSP/QFN
10 ______________________________________________________________________________________
Timing Circuits/Timing Diagrams
t
r
< 5ns
t
f
< 5ns
50%
0V
LOGIC
INPUT
R
L
COM_
GND
IN_
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
V
OUT
= V
N_ (
R
L
)
R
L
+ R
ON
V
N_
V+
t
OFF
0V
NO_
OR NC_
0.9 x V
0UT
0.9 x V
OUT
t
ON
V
OUT
SWITCH
OUTPUT
LOGIC
INPUT
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
V+
C
L
V+
V
OUT
MAX4754/MAX4754A
MAX4755/MAX4756/
MAX4756A
50%
Figure 1. Switching Time
50%
V+
0V
LOGIC
INPUT
V
OUT
0.9 x V
OUT
t
BBM
LOGIC
INPUT
R
L
GND
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
NO_
IN_
NC_
V
OUT
V+
V+
C
L
V
N_
COM_
MAX4754/MAX4754A
MAX4755/MAX4756/
MAX4756A
Figure 2. Break-Before-Make Interval
V
GEN
GND
COM_
C
L
V
OUT
V+
V
OUT
IN
OFF
ON
OFF
ΔV
OUT
Q = (ΔV
OUT
)(C
L
)
NC_
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
OFF
ON
OFF
IN
V
IL
TO V
IH
V+
R
GEN
IN_
OR NO_
MAX4754/MAX4754A
MAX4755/MAX4756/
MAX4756A
Figure 3. Charge Injection