Datasheet

MAX4737/MAX4738/MAX4739
4.5 Ω Quad SPST Analog Switches in UCSP
10 ______________________________________________________________________________________
Test Circuits/Timing Diagrams
50%
LOGIC
INPUT
R
L
COM_
GND
IN_
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
V
OUT
= V
COM
V
N_
V
OUT
V
IL
V
IH
t
OFF
0V
NO_
OR NC_
0.9 x V
0UT
0.9 x V
OUT
t
ON
V
OUT
SWITCH
OUTPUT
LOGIC
INPUT
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
V+
C
L
V+
MAX4737/
MAX4738/
MAX4739
(
R
L
R
L
- R
ON
)
Figure 1. Switching Time
LOGIC
INPUT
R
L2
GND
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
NO_
IN_
NC_
V
OUT2
V+
V+
C
L2
MAX4739
R
L1 C
L1
V
OUT1
V
COM1
V
COM2
50%
0.9 x V
0UT1
0V
LOGIC
INPUT
SWITCH
OUTPUT 2
(V
OUT2
)
0V
0.9 x V
OUT2
t
D
t
D
SWITCH
OUTPUT 1
(V
OUT1
)
COM2
COM1
V
IL
V
IH
Figure 2. Break-Before-Make Interval