Datasheet

Figure 2. Break-Before-Make Interval
Figure 3. Charge Injection
Figure 4. Channel Off/On-Capacitance
50%
V
IH
+ 0.5V
0
LOGIC
INPUT
V
OUT
0.9 x V
OUT
t
D
MAX4736
LOGIC
INPUT
R
L
GND
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
NO_ or NC_
IN_
NC_ or NO_
V
OUT
V+
V+
C
L
V
IN
COM_
t
r
< 5ns
t
f
< 5ns
V
GEN
GND
COM_
C
L
V
OUT
V+
V
OUT
IN
OFF
ON
OFF
∆V
OUT
Q = (∆V
OUT
)(C
L
)
OR NO_
NC_
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
OFF
ON
OFF
IN
V
INL
TO V
INH
V+
R
GEN
IN
MAX4736
CAPACITANCE
METER
NC_ OR
NO_
COM_
GND
IN_
V
INL
OR
V
INH
10nF
V+
f = 1MHz
V+
MAX4736
MAX4736 0.6Ω, Low-Voltage, Single-Supply, Dual SPDT
Analog Switch
www.maximintegrated.com
Maxim Integrated │ 8
Test Circuits/Timing Diagrams (continued)
Chip Information
TRANSISTOR COUNT: 379
PROCESS: CMOS