Datasheet

MAX4731/MAX4732/MAX4733
50 Ω, Dual SPST Analog Switches in UCSP
_______________________________________________________________________________________ 9
Test Circuits/Timing Diagrams (continued)
50%
V
IL
LOGIC
INPUT
R
L
300
Ω
IN_
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
(
R
L
)
V
N_
V
IH
t
OFF
0V
NO_
OR NC_
0.9 x V
OUT
0.9 x V
OUT
t
ON
V
OUT
SWITCH
OUTPUT
LOGIC
INPUT
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
V+
COM_
C
L
35pF
V+
V
OUT
MAX4731
MAX4732
MAX4733
GND
R
L
+ R
ON
t
r
< 5ns
t
f
< 5ns
V
OUT
= V
N_
Figure 2. Switching Time
50%
0.9 x V
0UT1
V+
0V
0V
LOGIC
INPUT
SWITCH
OUTPUT 2
(V
OUT2
)
0V
0.9 x V
OUT2
t
BBM
t
BBM
LOGIC
INPUT
R
L2
300
Ω
GND
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
NC2
IN2
IN1
NO1
V
OUT2
V+
V+
C
L2
35pF
V
N_
R
L1
300
Ω
V
OUT1
C
L1
35pF
COM1
COM2
SWITCH
OUTPUT 1
(V
OUT1
)
MAX4733
t
r
< 5ns
t
f
< 5ns
Figure 3. Break-Before-Make Interval (MAX4733 only)
V
GEN
GND
COM
C
L
1nF
V
OUT
V+
V
OUT
IN
OFF
ON
OFF
∆V
OUT
Q = (∆V
OUT
)(C
L
)
NC_
OR NO_
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
OFF
ON
OFF
IN
V
IL
TO V
IH
V+
R
GEN
IN_
MAX4731
MAX4732
MAX4733
Figure 4. Charge Injection