Datasheet

Power-Supply Bypassing
Power-supply bypassing improves noise margin and
prevents switching noise from propagating from the V+
supply to other components. A 0.1µF capacitor connect-
ed from V+ to GND is adequate for most applications.
Power-Supply Sequencing
and Overvoltage Protection
Caution: Do not exceed the absolute maximum rat-
ings because stresses beyond the listed ratings may
cause permanent damage to the device.
UCSP Package Considerations
For general UCSP package information and PC layout
considerations, please refer to the Maxim Application
Note (Wafer-Level Chip-Scale Package).
UCSP Reliability
The chip-scale package (UCSP) represents a unique
packaging form factor that may not perform equally to a
packaged product through traditional mechanical relia-
bility tests. UCSP reliability is integrally linked to the
user’s assembly methods, circuit board material, and
usage environment. The user should closely review
these areas when considering use of a UCSP package.
Performance through Operating Life Test and Moisture
Resistance remains uncompromised as it is primarily
determined by the wafer-fabrication process.
Mechanical stress performance is a greater considera-
tion for a UCSP package. UCSPs are attached through
direct solder contact to the user’s PC board, foregoing
the inherent stress relief of a packaged product lead
frame. Solder joint contact integrity must be consid-
ered. Information on Maxim’s qualification plan, test
data, and recommendations are detailed in the UCSP
application note, which can be found on Maxim’s web-
site at www.maxim-ic.com.
MAX4721/MAX4722/MAX4723
4.5 Ω Dual SPST Analog Switches in UCSP
_______________________________________________________________________________________ 9
Test Circuits/Timing Diagrams
50%
V
IL
LOGIC
INPUT
R
L
COM_
GND
IN_
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
V
OUT
= V
COM
V
N_
V
IH
t
OFF
0V
NO_
OR NC_
0.9 x V
0UT
0.9 x V
OUT
t
ON
V
OUT
SWITCH
OUTPUT
LOGIC
INPUT
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
V+
C
L
V+
V
OUT
MAX4721/
MAX4722/
MAX4723
(
R
L
R
L
- R
ON
)
Figure 1. Switching Time
LOGIC
INPUT
R
L2
GND
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
NO_
IN_
NC_
V
OUT2
V+
V+
C
L2
MAX4723
R
L1 C
L1
V
OUT1
V
COM1
V
COM2
50%
0.9 x V
0UT1
V
IH
V
IL
0V
LOGIC
INPUT
SWITCH
OUTPUT 2
(V
OUT2
)
0V
0.9 x V
OUT2
t
D
t
D
SWITCH
OUTPUT 1
(V
OUT1
)
COM2
COM1
Figure 2. Break-Before-Make Interval