Datasheet

MAX4721/MAX4722/MAX4723
4.5 Ω Dual SPST Analog Switches in UCSP
10 ______________________________________________________________________________________
t
skew_i
90%
50%
10%
90%
50%
10%
t
fi
INPUT A
INPUT A-
t
ri
t
skew_o
90%
50%
10%
90%
50%
10%
t
fo
OUTPUT B
OUTPUT B-
t
ro
B-
C
L
A-
R
s
A
B
C
L
TxD+
TxD-
R
s
R
s
= 39Ω
C
L
= 50pF
DELAY DUE TO SWITCH FOR RISING INPUT AND RISING OUTPUT SIGNALS.
DELAY DUE TO SWITCH FOR FALLING INPUT AND FALLING OUTPUT SIGNALS.
CHANGE IN SKEW THROUGH THE SWITCH FOR OUTPUT SIGNALS.
CHANGE IN SKEW THROUGH THE SWITCH FOR INPUT SIGNALS.
|t
skew_i
|
|t
skew_o
|
|t
fo -
t
fi
|
|t
ro -
t
ri
|
Figure 3. Input/Output Skew Timing Diagram
Test Circuits/Timing Diagrams (continued)