Datasheet

MAX4695
Low-Voltage, 60Ω Dual
SPDT Analog Switch in Thin QFN
8 _______________________________________________________________________________________
Test Circuits/Timing Diagrams
50%
V
INH
V
INL
LOGIC
INPUT
V
OUT
0.9 × V
OUT
t
D
LOGIC
INPUT
R
L
300Ω
GND
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
NO_
IN_
NC_
V
OUT
V+
V+
C
L
35pF
V
N_
V
IN_
COM_
MAX4695
0.9 × V
0UT
Figure 3. Break-Before-Make Interval
V
GEN
GND
COM_
C
L
1nF
V
OUT
V+
V
OUT
IN
OFF
ON
OFF
∆V
OUT
Q = (∆V
OUT
)(C
L
)
NC_
OR NO_
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
OFF
ON
OFF
IN
V
INL
TO V
INH
V+
R
GEN
IN
MAX4695
Figure 4. Charge Injection
t
r
< 5ns
t
f
< 5ns
50% 50%
V
INL
LOGIC
INPUT
R
L
300Ω
COM_
GND
IN_
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
V
OUT
= V
N_ (
R
L
)
R
L
+ R
ON
V
INH
t
OFF
0
NO_
OR NC_
0.9 × V
0UT
0.9 × V
OUT
t
ON
V
OUT
SWITCH
OUTPUT
LOGIC
INPUT
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
V+
C
L
35pF
V+
V
OUT
MAX4695
V
N_
V
IN_
Figure 2. Switching Time