Datasheet

MAX4675/MAX4676
3Ω Single SPST Analog Switches
_______________________________________________________________________________________ 7
Applications Information
Overvoltage Protection
Proper power-supply sequencing is recommended for all
CMOS devices. Do not exceed the absolute maximum
ratings because stresses beyond the listed ratings can
cause permanent damage to the devices. Always
sequence V+ on first, then V-, followed by the logic
inputs, NO, NC, or COM. If proper power-supply
sequencing is not possible, add two small-signal diodes
(D1, D2) in series with the supply pins (Figure 1). Adding
diodes reduces the analog signal range to one diode
drop below V+ and one diode drop above V- but does
not affect the devices’ low switch resistance and low
leakage characteristics. Device operation is unchanged,
and the difference between V+ and V- should not
exceed 12V.
Power-supply bypassing improves noise margin and
prevents switching noise from propagating from the V+
supply to other components. A 0.1µF capacitor connect-
ed from V+ to GND is adequate for most applications.
V+
V-
V
g
Figure 1. Overvoltage Protection Using External Blocking
Diodes
t
r
< 20ns
t
f
< 20ns
50% 50%
0
LOGIC
INPUT
R
L
300Ω
COM
GND V-
V-
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
V
OUT
= V
COM (
R
L
)
R
L
+ R
ON
SWITCH
INPUT
IN
+3V
t
OFF
0
NO
OR NC
SWITCH
OUTPUT
0.9 x V
0UT
0.9 x V
OUT
t
ON
V
OUT
SWITCH
OUTPUT
LOGIC
INPUT
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
V+
C
L
35pF
V+
V
OUT
MAX4675
MAX4676
Figure 2. Switching Time
Timing Diagrams/Test Circuits
Figure 3. Charge Injection
V
GEN
GND
COM
C
L
V
OUT
V-
V-
V+
V
OUT
IN
OFF
ON
OFF
∆V
OUT
Q = (∆V
OUT
)(C
L
)
NC
OR NO
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
OFF
ON
OFF
IN
V
IN
= 3.0V
V+
R
GEN
IN
MAX4675
MAX4676