Datasheet

MAX4667/MAX4668/MAX4669
2.5
, Dual, SPST,
CMOS Analog Switches
_______________________________________________________________________________________ 9
LOGIC
INPUT
V-
-15V
R
L
100
NO_
OR NC_
GND
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
V
O
= V
COM (
R
L
)
R
L
+ R
ON
SWITCH
INPUT
IN_
COM_
SWITCH
OUTPUT
t
r
< 20ns
t
f
< 20ns
50%
0V
+3V
t
OFF
0V
0.9V
0
0.9V
0
t
ON
V
O
SWITCH
OUTPUT
LOGIC
INPUT
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
VL
V+
C
L
35pF
+5V
+15V
V
O
V
COM_
0
REPEAT TEST FOR EACH SWITCH. FOR LOAD
CONDITIONS, SEE
ELECTRICAL CHARACTERISTICS.
MAX4667
MAX4668
MAX4669
Figure 2. Switching-Time Test Circuit
V
GEN
GND
NC OR
NO
C
L
V
O
-15V
V-
V+
V
O
V
IN
OFF
ON
OFF
V
O
Q = (V
O
)(C
L
)
COM
+5V
V
IN
DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
OFF
ON
OFF
V
IN
V
IN
= +3V
+15V
R
GEN
IN
V
L
MAX4667
MAX4668
MAX4669
Figure 3. Charge-Injection Test Circuit
Test Circuits/Timing Diagrams