Datasheet
*EP = Exposed pad.
PART TEMP RANGE PIN-PACKAGE
MAX4582LESE -40°C to +85°C 16 Narrow SO
MAX4582LEEE -40°C to +85°C 16 QSOP
MAX4582LETE -40°C to +85°C 16 TQFN-EP* (4mm x
4mm)
MAX4583LESE -40°C to +85°C 16 Narrow SO
MAX4583LEEE -40°C to +85°C 16 QSOP
MAX4583LETE -40°C to +85°C 16 TQFN-EP* (4mm x
4mm)
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
V
CC
X2
X1
X0
X3
A
B
C
X4
X6
X
X7
X5
ENABLE
GND
GND
MAX4581L
SO/QSOP
LOGIC
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
V
CC
Y
X
X1
X0
A
B
C
Y1
Y0
Z1
Z
Z0
ENABLE
GND
GND
MAX4583L
SO/QSOP
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
V
CC
X2
X1
X
X0
X3
A
B
Y0
Y2
Y
Y3
Y1
ENABLE
GND
GND
MAX4582L
SO/QSOP
LOGIC
TOP VIEW
MAX4581L/MAX4582L/
MAX4583L
Low-Voltage, CMOS Analog
Multiplexers/Switches
www.maximintegrated.com
Maxim Integrated
│
12
Chip Information
TRANSISTOR COUNT: 219
PROCESS: CMOS
Ordering Information (continued)
Pin Congurations/Functional Diagrams (continued)
Package Information (continued)
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
DOCUMENT
NO.
LAND
PATTERN
NO.
16 Narrow
SO
S16-3 21-0041
Refer to
Application
Note 1891
16 QSOP E16-4 21-0055
16 TQFN-EP T1644-4 21-0139