Datasheet

MAX4564
Low-Voltage, Dual-Supply,
SPDT Analog Switch with Enable
9
Maxim Integrated
t
r
< 5ns
t
f
< 5ns
50%
V
INL
LOGIC
INPUT
R
L
COM
GND
IN
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
V
IN
V
INH
t
OFF
0
NO
OR NC
0.9 × V
0UT
0.9 × V
OUT
t
ON
V
OUT
SWITCH
OUTPUT
LOGIC
INPUT
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
V+
C
L
35pF
V+
V
OUT
MAX4564
V-
Figure 2. Switching Time
50%
V
INH
V
INL
LOGIC
INPUT
V
OUT
0.9 × V
OUT
t
D
LOGIC
INPUT
R
L
GND
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
NO
IN
NC
V
OUT
V+
V+
C
L
35pF
V
N
COM
MAX4564
V-
Figure 3. Break-Before-Make Interval
V
GEN
GND
COM
C
L
V
OUT
V+
V
OUT
IN
OFF
ON
OFF
∆V
OUT
Q = (∆V
OUT
)(C
L
)
NC
OR NO
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
OFF
ON
OFF
IN
V
IL
TO V
IH
V+V-
IN
MAX4564
Figure 4. Charge Injection
Test Circuits/Timing Diagrams (continued)