Datasheet

MAX4561/MAX4568/MAX4569
±15kV ESD-Protected, Low-Voltage,
SPDT/SPST, CMOS Analog Switches
8
t
r
< 20ns
t
f
< 20ns
50%
0
LOGIC
INPUT
R
L
COM
GND
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
V
OUT
= V
COM (
R
L
)
R
L
+ R
ON
SWITCH
INPUT
IN
+3V
t
OFF
0
NO
OR NC
SWITCH
OUTPUT
0.9 x V
0UT
0.9 x V
OUT
t
ON
V
OUT
SWITCH
OUTPUT
LOGIC
INPUT
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
V+
C
L
V+
V
OUT
MAX4561
MAX4568
MAX4569
Figure 1. Switching Time
50%
+3V
0
LOGIC
INPUT
SWITCH
OUTPUT
(V
OUT
)
0.9 x V
OUT
0.9 x V
OUT
t
BBM
LOGIC
INPUT
R
L
GND
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
NO
IN
NC
V
OUT
V+
V+
C
L
+3V
COM
MAX4561
Figure 2. Break-Before-Make Interval
V
GEN
GND
COM
C
L
V
OUT
V+
V
OUT
+3V
∆V
OUT
Q = (∆V
OUT
)(C
L
)
NC
OR NO
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
0
V
IN
= LOGIC INPUT
V+
R
GEN
IN
MAX4561
MAX4568
MAX4569
0
+3V
IN
Figure 3. Charge Injection
Test Circuits/Timing Diagrams